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13 Commits (482f0489a3a502b11d4be3dd6f7a67bc5feacf0c)

Author SHA1 Message Date
Iacob_Liviu 482f0489a3 scripts: Merge adi_env.tcl into a single file 
Move the new adi_env.tcl file from hdl/projects/scripts into hdl/scrips
 2022-08-08 13:52:54 +03:00
Iulia Moldovan 0c0617d49e libraries: Update modules according to guideline 
* Added header license for the files that didn't have
* Modified parentheses
* Removed extra spaces at the end of lines
* Fixed parameters list to be each parameter on its line
* Deleted lines after endmodule and consecutive empty lines
* Fixed indentation

Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
 2022-06-28 18:06:56 +03:00
Nick Pillitteri c1721e18dd account for ADI_VIVADO_IP_LIBRARY global variable when adding subcores 2022-03-24 16:29:49 +02:00
Adrian Costina 591a23156b Makefiles: Update header with the appropriate license 2021-09-16 16:50:53 +03:00
AndreiGrozav b4c5031272 axi_pulse_gen: Fix typo introduced in c235e5e58 2021-05-10 13:26:30 +03:00
AndreiGrozav c235e5e583 axi_pwm_gen: Initial commit 
axi_pwm_gen is based on util_pulse_gen, it introduces the option of
phase option between pulses(PWMs) and external synchronization.
Documentation available at
https://wiki.analog.com/resources/fpga/docs/axi_pwm_gen
 2021-05-07 19:09:32 +03:00
Istvan Csomortani a49138c257 axi_laser_driver: Add support for Intel platforms 2019-10-02 15:32:17 +03:00
Istvan Csomortani d4200aee9a axi_pulse_gen_regmap: Rename the clk output to clk_out 2019-08-08 14:26:07 +03:00
Istvan Csomortani f1403aa593 axi_pulse_gen: Update constraint file 
- add missing false paths
 - change the bus skew constraint to a false path, for some reason the
   tool does not change the path's requirement after a set_bus_skew
   constraint
 2019-08-08 14:26:07 +03:00
Istvan Csomortani 3a7d0698a8 axi_pulse_gen: Registers should be placed at front of the register space 
Because this register map will be integrated into other IPs too, make
sure that the registers are places in the absolute front of the register
space.
 2019-08-08 14:26:07 +03:00
Arpadi fe09acaa2f up_axi_update: ADDRESS_WIDTH parameter is now a localparam 
ADDRESS_WIDTH is now AXI_ADDRESS_WIDTH - 2;
up_axi instantiations will set AXI_ADDRESS_WIDTH instead of ADDRESS_WIDTH;
 2019-07-26 11:58:58 +03:00
Istvan Csomortani 363494ab9c library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl 2019-06-29 06:53:51 +03:00
Istvan Csomortani 0e7b38ebcf axi_pulse_gen: Initial commit 
The axi_pulse_gen is a generic PWM generator, which can be configured
through an AXI Memory Mapped interface.

The current register map look like follows:

  0x00 - VERSION
  0x04 - ID
  0x08 - SCRATCH
  0x0C - IDENTIFICATION - 0x504c5347 which stands for 'PLSG' in ASCII
  0x10 - CONFIGURATION - contains reset and load bits
  0x14 - PULSE_PERIOD
  0x18 - PULSE_WIDTH

Also update all the other modules, which instantiate the util_pulse_gen.
 2019-03-20 08:21:22 +00:00