ac2e5a9dac
constraints: Update constraints
...
Xilinx recommends that all synchronizer flip-flops have
their ASYNC_REG property set to true in order to preserve the
synchronizer cells through any logic optimization during synthesis
and implementation.
2017-02-24 13:43:32 +02:00
1156aeac16
ad_sysref_gen: Update SYSREF related constraints
2016-12-19 18:07:05 +02:00
8d799d0316
fmcjesdadc1: Intergrate ad_sysref_gen into project
2016-12-19 13:37:29 +00:00
a54092c9bb
fmcjesdadc1: Update projects to xcvr framework
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This commit contains modifications for Xilinx only
2016-11-10 10:59:52 +02:00
59fbd99fdb
fmcjesdadc1: Added clock constraint for the ADC path
2016-01-22 15:46:20 +02:00
78fe05120b
fmcjesdadc1: Updated KC705 project
2015-09-24 19:14:48 +03:00
c7e4ba5083
fmcjesdadc1: Updated KC705 to the latest flow
2015-03-30 18:07:47 +03:00
9f3461b130
fmcjesdadc1: Added support for KC705
2014-09-02 18:02:25 +03:00
Istvan Csomortani
Adrian Costina