91782989ad
pzsdr: ccpci: Set IO standard to LVCMOS33 for banks 12 and 13
...
The IO voltage for bank 12 and 13 is 3.3V on the PCIe carrier. Set the
IOSTANDARD of the pins on these banks accordingly.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-08-05 18:31:40 +02:00
418217dd10
pzsdr: Remove LED and button signals from PCIe carrier
...
Only the FMC carrier and the breakout board do have push buttons and LEDs.
They are not present on the PCIe carrier. So move the constraints to a
separate file that can be included by the projects that need them and
remove all LED and button related signals from the PCIe project.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-08-05 18:31:40 +02:00
3cff0fa7dc
pzsdr: ccpci: Use PL SPI and GPIO peripherals
...
To be able to access the GPIO pins and the SPI port through the PCIe bridge
we need to use the PL SPI and GPIO controllers rather than the PS
controllers. Adjust the sytem_top.v accordingly so that the PL peripherals
are connected to the external pins.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-08-05 18:29:42 +02:00
5faf4c4976
cleanup: Don't need Makefiles specific to xilinx/altera libraries. Top Makefile covers them
2016-08-05 16:27:52 +03:00
d60bce654c
Makefiles: Updated Makefiles so they run correctly with gnuwin32 tools
2016-08-05 15:16:04 +03:00
cb23ba8bb7
make- script needs update
2016-08-04 14:17:04 -04:00
e42b4ea378
hdlmake- updates
2016-08-04 13:28:25 -04:00
2b7c976be5
xcvr- altera/xilinx split
2016-08-04 13:26:10 -04:00
ed9e92621c
daq2- spi+xcvr address conflict
2016-08-04 10:50:31 -04:00
cba53774ca
axi_dmac: Don't add CDC constraints when all clocks are synchronous
...
When all clocks are synchronous there are no synchronizers and the
constraint for the CDC registers can't find any cells which generates a
warning. To avoid this don't add CDC constraints when all the clocks are
synchronous.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-08-02 19:30:24 +02:00
999eccc134
daq3: Update A10GX project to Quartus 16.0
2016-08-01 16:19:43 +03:00
9a563de8ff
daq2: A10GX updated project to Quartus 16.0
...
- connected directly axi_ad9680 to xcvr_core, skipping axi_jesd_xcvr
2016-08-01 15:09:53 +03:00
52ae3ddd6c
a10gx: Updated common files to 16.0
2016-08-01 15:08:12 +03:00
aece3f5555
axi_ad9680: Update IP core
...
- added signals so that AD9680 can be connected to altera's xcvr core through an avalon streaming sink
- added DEVICE_TYPE parameter in _hw.tcl, set to 1 for altera
2016-08-01 15:05:30 +03:00
7ca8e10004
make: Update Make files
2016-08-01 14:24:48 +03:00
a0ae791395
hdl-vivado-2016.2: Update axi_jesd_gt
...
Infer AXI bus interfaces separately.
2016-08-01 13:53:18 +03:00
af4c43b6e1
hdl-vivado-2016.2: Update fmcomms2 and pzsdr base design
2016-08-01 13:49:12 +03:00
fbe3d75eb0
cosmetics: Delete trailing whitespace characters
2016-08-01 13:46:46 +03:00
b99117e686
up_axi: Same cycle BVALID/READY fails on Altera
...
The Qsys interconnect does not handle the assertion of BVALID on the
same cycle as [A]WREADY. Add a single cycle of delay to prevent
deadlocks.
Similar to:
2817ccdb22
2016-08-01 12:17:10 +03:00
58b220ba81
ad_tdd_control: Add an on/off switch to the receive datapath
...
For a more robust control, add an on/off switch to the receive datapath too,
in order to filter out transition noises.
2016-08-01 11:49:27 +03:00
7988d2c7a2
adi_ip: remove duplicated errored auto address maps & interfaces
2016-07-29 12:32:19 -04:00
4aa506de8d
adxcvr- added a space?
2016-07-29 09:38:08 -04:00
71dad14e0e
axi_adcfifo- disable auto infer mess-up
2016-07-29 09:37:17 -04:00
9952a94efb
hdl-vivado-2016.2- ip version updates
2016-07-28 13:44:57 -04:00
39ff059ef6
hdl-vivado-2016.2- productivity decimated again!
2016-07-28 13:44:57 -04:00
d5d61ff518
hdl-vivado-2016.2- productivity decimated again!
2016-07-28 13:44:57 -04:00
52b544bb66
hdl-vivado-2016.2- auto infer bus interfaces
2016-07-28 13:44:57 -04:00
6ffe59728b
hdl-vivado-2016.2- update
2016-07-28 13:44:57 -04:00
3b2bde2fa1
hdl-vivado-2016.2- min. addr-space requirement
2016-07-28 13:44:57 -04:00
3384d384d3
hdl-vivado-2016.2- infer bus interfaces separately
2016-07-28 13:44:57 -04:00
c316f0dfea
ad9144- synthesis warnings fix
2016-07-28 13:44:57 -04:00
8a2734b43e
up_dac_common- typo- unf register reset
2016-07-28 13:44:57 -04:00
08f4ba24d5
usb_fx3: Switch PS7 UART to UARTLITE to communicate with the FX3 board
2016-07-28 15:21:38 +03:00
6ebb32a194
library axi-slave missing protection signal added
2016-07-22 12:54:27 -04:00
39a5534e00
hdlmake- updates
2016-07-21 16:10:38 -04:00
6df5ba1a7a
daq2- adxcvr version
2016-07-21 16:09:33 -04:00
5c91e41da8
ad9680- sof + sample delineation
2016-07-21 16:09:33 -04:00
db6d5f509f
library/common- xcvr interface logic
2016-07-21 16:09:33 -04:00
75864f0ce5
util_adxcvr- add constraints file
2016-07-21 16:09:33 -04:00
1435c5f7f7
util_adxcvr- add clock buffers, rst-done, rate on usrclk
2016-07-21 16:09:33 -04:00
8e04e70791
axi_adxcvr- status output for jesd ip
2016-07-21 16:09:33 -04:00
1f25d7f637
axi_adxcvr- self-disable based on num of lanes
2016-07-21 16:09:33 -04:00
c797a579f1
util_adxcvr- rstdone on usrclk2
2016-07-21 16:09:33 -04:00
4532e5c0cb
fmcomms11- support iq mode
2016-07-21 11:58:03 -04:00
ced36f6159
up-dac- support iq mode
2016-07-21 11:58:03 -04:00
3a1ecb7463
ad9162- support iq mode
2016-07-21 11:58:03 -04:00
040f72d172
ad_mul_u16: Delete unused module
2016-07-20 14:17:04 +03:00
2dd6bb0cb8
up_drp_cntrl: Delete unused module
2016-07-20 14:17:04 +03:00
af9915b060
up_axis_dma_*: Delete unused modules
2016-07-20 14:17:04 +03:00
df43ca9332
ad_axis_dma_*: Delete unused modules
2016-07-20 14:17:04 +03:00
Lars-Peter Clausen
Adrian Costina
Rejeesh Kutty
Istvan Csomortani
Matthew Fornero
Shrutika Redkar