* jesd204b: add bonding clocks feature (fix for some routing issues)
* intel/adi_jesd204: bonding clock feature invisible in QSYS GUI if number of lanes is less than 6
* intel/adi_jesd204: clock network option renamed according to intel documentation
* intel/adi_jesd204: Hide BONDING_CLOCKS_EN parameter in RX mode
Co-authored-by: István Csomortáni <Csomi@users.noreply.github.com>
In Subclass 1 mode, we need to use a separate clock (device clock) to
drive the link and transport layer of the interface. Implement the
required infrastructure for this scenario.
The clock domain crossing will be done in by the TX|RX_FIFO in the PCS.
cycollineau
Istvan Csomortani