4 Commits (4a772265a9dfd031e36df5a6f6e8639c84dad61f)

Author	SHA1	Message	Date
Adrian Costina	b01cf35cf7	axi_adcfifo: Fix constraints to apply also to Ultrascale devices ... Used IS_SEQUENTIAL instead of PRIMITIVE_SUBGROUP==flop to identify ff related constraints	2018-09-07 17:44:47 +03:00
AndreiGrozav	c313c67585	axi_adcfifo_constr.xdc: Add missing backslash to command	2018-04-11 15:09:54 +03:00
Lars-Peter Clausen	55daa786fa	axi_adcfifo: Add missing constraints ... Add missing timing exceptions on paths between the DMA and DDR clock domains. All these paths are properly synchronized using CDC in the HDL, but are missing timing exceptions in the XDC file. This can lead to timing errors when building a design using the axi_adc_fifo. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>	2017-09-13 19:52:48 +02:00
Istvan Csomortani	3cbbc771a8	axi_adcfifo: Move IP to library/xilinx	2016-09-15 11:36:47 +03:00