4a772265a9
Update Quartus Prime version from 19.3.0 to 20.1.0
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adi_project_intel.tcl: Change quartus version to 20.1.0.
library: Set qsys version so that IP instances won't require a specific version.
2021-03-08 11:29:33 +02:00
1099badaf4
ad9082_fmca_ebz:zc706: Initial version
2021-03-05 15:54:23 +02:00
2213527f29
ad9082_fmca_ebz:zcu102: Initial version
2021-03-05 15:54:23 +02:00
f56e3c305b
ad9082_fmca_ebz:vcu118: Initial version
2021-03-05 15:54:23 +02:00
6b13b32f24
ad9081_fmca_ebz: Workaround DMA bug when bus size equals max burst size
2021-03-04 11:13:29 +02:00
677c154134
adrv9001/zcu102/cmos: Loosen up clock skew constraints to match LVDS settings
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Set the same inter clock skew characteristics as used in LVDS mode. The
physical lanes/routes are common on both modes.
2021-03-04 11:13:10 +02:00
03de08609b
fmcomms2/zed: Disable unused TDD to save space and timing
2021-03-04 11:13:10 +02:00
0dd3173547
adrv9001/zc706: Initial commit
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The project supports CMOS interface only.
VADJ on the ZC706 must be programmed to 1.8V
Instructions can be found here:
https://www.xilinx.com/Attachment/ZC706_Power_Controllers_Reprogramming_Steps.pdf
https://forums.xilinx.com/t5/Xilinx-Evaluation-Boards/ZC706-Doesn-t-work-with-VADJ-at-1-8v/td-p/430086
2021-03-03 09:03:03 +02:00
3be5137aec
cn0540/cora: Remove multicycle constraint
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Design uses 80MHz spi_clk which does not require
special considerations
2021-02-18 14:14:16 +02:00
701e5f6515
scripts/adi_board.tcl: Add simulation support
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This will allow building base test harnesses and place on top of them
existing block designs for simulation purposes.
Test harnesses will contain basic functionality like
- clock and reset generators
- AXI master to aid register access of the cores.
- memory model of the DDR
- interrupt controller
Existing procedures (ad_mem_hp0_interconnect, ad_cpu_interconnect, ... ) will
connect to this harness as they do to a real base design.
2021-02-12 16:21:10 +02:00
0374a7c1ac
ad9081_fmca_ebz/vcu118: Added common 204C use cases as example
2021-02-05 15:24:15 +02:00
ddd8a14790
ad9081_fmca_ebz: Remove system reset from Xilinx PHY
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Reset in device clock domain caused timing failures.
Since link reconfiguration is not supported the reset is not required.
2021-02-05 15:24:15 +02:00
af3e1c7003
ad9081_fmca_ebz/a10soc: Np 12 support
2021-02-05 15:24:15 +02:00
f73ed741c9
fmcadc5: Connect link clock to second JESD link layer
2021-02-05 15:24:15 +02:00
3f2f88ebbc
ad_fmclidar1_ebz: Set bits per sample towards the DMA interface
2021-02-05 15:24:15 +02:00
dafdd1c1e9
ad9208_dual_ebz: Use ad_xcvrcon procedure to connect device clock
2021-02-05 15:24:15 +02:00
bb9eafceef
ad9081_fmca_ebz/zcu102: Add case analysis to select correct out clock frequency
2021-02-05 15:24:15 +02:00
d0f8a81b2f
ad9081_fmca_ebz: Np 12 support
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204B functional
204C functional
2021-02-05 15:24:15 +02:00
454b900f90
jesd204: Xilinx: NP=12 support
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To support deterministic latency with non-power of two octets per frame
(F=3,6) the interface width towards the transport layer must be resized
to match integer multiple of frames.
e.g Input datapath width = 4; Output datpath width = 6;
for F=3 one beat contains 2 frames
for F=6 one beat contains 1 frame
The width change is realized with a gearbox.
Due the interface width change the single clock domain core is split
in two clock domains.
- Link clock : lane rate / 40 for input datapath width of 4 octets 8b10b
- lane rate / 20 for input datapath width of 8 octets 8b10b
- lane rate / 66 for input datapath width of 8 octets 64b66b
- Device clock : Link clock * input data path width / output datapath width
Interface to transport layer and SYSREF handling is moved to device clock domain.
The configuration interface reflects the dual clock domain.
If Input and Output datapath width matches, the gearbox is no longer
required, a single clock can be connected to both clocks.
2021-02-05 15:24:15 +02:00
7be66b63c1
adrv9009zu11eg:fmcomms8: Fix lane swapping for TX channels 0 and 1 on the FMCOMMS8
2021-02-05 15:07:09 +02:00
6d504d14cf
fmcomms8: zcu102: Fix lane swapping
2021-02-05 15:07:09 +02:00
0fd5590e56
ad9081_fmca_ebz: a10soc: Initial version
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Parametrizable project with default profile of:
M=8 L=4 SampleRate=250 MSPS
LaneRate=10 Gbps
2021-02-05 10:24:59 +02:00
6e6c51dd27
common/a10soc: Bridge support
2021-02-05 10:24:59 +02:00
f0b753321a
common/intel: Add util_adcfifo integration script
2021-02-05 10:24:59 +02:00
3041e77659
ad40xx/zed: Update constraints
2021-02-04 11:04:32 +02:00
05469a011c
ad40xx/xilinx: Activate AXI_SLICE_SRC for the DMA
2021-02-04 11:04:32 +02:00
dd4c8d6807
adrv9001/zcu102: Add debug header
2021-01-26 15:22:41 +02:00
728904af09
adrv9001/zcu102: Run postRoutePhysOpt to close Rx1 to Rx2 path timing
2021-01-26 15:22:41 +02:00
bae7e48c50
adrv9001/common: Run DMAs @ 100MHz
2021-01-26 15:22:41 +02:00
f68c222489
cn0501/coraz7s: Fix sysid
2021-01-22 15:40:37 +02:00
bb44e5399f
adrv9001/zed: Connect TDD sync to PMOD JA1
2021-01-20 13:00:01 +02:00
3918d43cd1
adrv9001/zcu102: Add TDD sync to PMOD0 J55.1
2021-01-20 13:00:01 +02:00
fe9f72db9c
adrv9001/common: Export TDD mode signal
2021-01-20 13:00:01 +02:00
18b2a8b0a7
adrv9001/zed: Add TDD support
2021-01-20 13:00:01 +02:00
0c2745361b
adrv9001/zcu102: Add TDD support
2021-01-20 13:00:01 +02:00
6f2f2b8626
makefile: Regenerate make files
2021-01-20 01:02:56 +02:00
da61515d41
ad40xx: Fix bd.tcl script
2021-01-20 01:02:56 +02:00
acbbd4636a
sysid: Upgrade framework, header/ip are now at 2/1.1.a
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Unify tcl scripts; rename adi_pd_intel.tcl to adi_pd.tcl
add git branch to internal use area; update log prints;
update xilixn projects; fix cn0506 sysid script;
2021-01-20 01:02:56 +02:00
da9828a63e
ad9081:zcu102: Expose parameters to environment
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Allow setting project parameters from the environment.
2021-01-19 17:10:08 +02:00
235fb4859a
usrpe31x: Use adi_project_create instead of adi_project
2021-01-15 15:26:43 +02:00
f1421c91ee
sidekiqz2: Use adi_project_create instead of adi_project
2021-01-15 15:26:43 +02:00
f68393ecb9
adrv936x: Use adi_project_create instead of adi_project
2021-01-15 15:26:43 +02:00
3e237459e3
pluto: Use adi_project_create instead of adi_project
2021-01-15 15:26:43 +02:00
d9639db991
m2k: Use adi_project_create instead of adi_project
2021-01-15 15:26:43 +02:00
e41ba7f6f5
adrv9009zu11eg: Use adi_project_create instead of adi_project
2021-01-15 15:26:43 +02:00
9ec3408c79
adi_project_xilinx: Fix the adi_project process
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In most of the standalone projects the generic project creation flow is not followed. The project's device
is defined manualy. This fix makes sure that those projects still builds without an issue.
NOTE: In these case we should use adi_project_create directly in system_project.tcl.
2021-01-15 15:26:43 +02:00
b9ac8df503
project-xilinx.mk: Add *.hbs to clean list
2021-01-15 13:50:53 +02:00
067b57d404
vc707: Fix mdio intf
2021-01-15 13:50:53 +02:00
c54552d823
adi_project_xilinx: Add env var
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add ADI_DISABLE_MESSAGE_SUPPRESION which disables
adi_xilinx_msg.tcl
projects/scripts/adi_project_xilinx.tcl
2021-01-15 13:50:53 +02:00
ead4513ad6
adi_xilinx_msg: Downgrade Synth 8-2490
2021-01-15 13:50:53 +02:00
stefan.raus
Laszlo Nagy
Sergiu Arpadi
Adrian Costina
Istvan Csomortani