5 Commits (4a783d523dd105cd3143ce7cace0dba07c446f71)

Author	SHA1	Message	Date
Istvan Csomortani	7876c8ffa4	axi_ad9684: Add loaden and phase ports for altera support	2016-12-06 15:24:20 +02:00
AndreiGrozav	91995c082d	axi_ad9684: Fixed up_drp_*data width	2016-10-12 13:20:26 +03:00
Istvan Csomortani	ad16aec101	axi_ad9684: Fix SERDES modules	2016-09-26 11:14:35 +03:00
Rejeesh Kutty	46eddd04be	library: port updates on mmcm	2016-03-22 12:50:59 -04:00
Istvan Csomortani	c6cfd1a2b6	axi_ad9684: Initial check in	2016-01-19 11:13:45 +02:00