033713ccb5
Add cordic demodulator module
...
The cordic_demod module takes in phase and data on s_axis interface then
performs a cordic demodulation and outputs the resulting I and Q component
data on the m_axis interface.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 17:21:35 +02:00
cefbe3a0ff
scripts/adi_ip.tcl: Add option to specify reset interface direction
...
Allow to specify the direction of the reset signal for a interface, this is
useful if the core itself generates the reset signal.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 17:21:35 +02:00
6b9906b22b
Refresh Makefiles
...
Re-generate the Makefiles after a small update to the generation script:
- Entries are sorted alphabetically
- Empty dependency lines are skipped
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 14:21:54 +02:00
ebbc0c6ed5
fmcomms5: zc706, removed debug related ila, as the pins were removed from the AD9361 IP
2015-05-21 14:19:22 +03:00
5ac7ebb8a3
axi_mc_*: Removed delay pins from up_adc_common
2015-05-21 14:03:58 +03:00
598ece4c8d
axi_ad9361/tdd: Update tdd related logic
...
+ TDD pointers and counter width is 24
+ Change TDD control ports name to 'enable' and 'txnrx'
+ Fix constraints
+ Rx or Tx only mode is controlled by a mode enable and a operation mode specifier bit
2015-05-21 13:39:48 +03:00
a047d3990a
fmcadc2_vc707: Fix interrupts
...
+ Remove some trailing whitespaces
+ Fix interrupt connections
2015-05-21 11:03:16 +03:00
99f9a75dfb
ad9434_zc706: Fix SPI interface
2015-05-21 11:00:04 +03:00
e1d3e889ba
fmcadc2_vc707: Fix interrupts
...
+ Remove some trailing whitespaces
+ Fix interrupt connections
2015-05-21 10:56:30 +03:00
19b094cab5
daq2/a10gx- added jesd align
2015-05-20 15:39:27 -04:00
465f7dff88
library/util_jesd_align -added
2015-05-20 15:38:43 -04:00
9762c65868
library- jesd-align port name change
2015-05-20 14:25:21 -04:00
f1c30ac225
daq2/a10gx- qsys updates
2015-05-20 14:24:49 -04:00
4927ca85c2
projects- jesd-align port name change
2015-05-20 14:24:26 -04:00
da0409b5a6
library- qsys components
2015-05-20 11:51:50 -04:00
9b425736ac
library: altera ip modifications
2015-05-20 10:41:21 -04:00
0f32b25fcc
Update README.md
...
Add FPGA vendor names
2015-05-20 17:38:08 +03:00
74eb3cb11d
Update README.md
...
Add section title Documentation and support
2015-05-20 17:17:23 +03:00
d48d3f4aa3
scripts/ip-alt- added
2015-05-20 09:11:18 -04:00
7c126d74db
enable/txnrx- tdd changes
2015-05-20 10:46:06 +03:00
41d45b310f
Update README.md
...
+ Add note about current status.
+ Add links for tools.
+ Use embedded links
2015-05-20 10:20:53 +03:00
52b6077a46
a10gx- 15.0 updates
2015-05-19 15:12:23 -04:00
e918588a4b
library: remove axi-min-size parameter
2015-05-19 13:07:48 -04:00
4fb1be0672
ad9680: delay changes
2015-05-19 12:53:56 -04:00
af7afd7366
ad9671: delay changes
2015-05-19 12:53:56 -04:00
09a05fe9d8
ad9652: delay changes
2015-05-19 12:53:56 -04:00
13156593f8
ad9643: delay changes
2015-05-19 12:53:56 -04:00
c8d3c04a05
ad9625: delay changes
2015-05-19 12:53:56 -04:00
f53204f9f9
ad9467: delay changes
2015-05-19 12:53:56 -04:00
0805da3b6b
fmcomms2/rfsom- enable dac delay
2015-05-18 16:45:54 -04:00
fe0ceb2530
delay-cntrl updates
2015-05-18 15:23:10 -04:00
304a202d67
delay-cntrl updates
2015-05-18 14:57:05 -04:00
2e257db109
delay-cntrl updates
2015-05-18 14:53:24 -04:00
3e51d29f75
enable/txnrx- tdd changes
2015-05-18 14:28:20 -04:00
0877c252ad
delay-cntrl changes
2015-05-18 14:28:20 -04:00
2bad47cf4f
delay-cntrl: up-clk, direct access + tx
2015-05-18 14:28:20 -04:00
6e047f78c6
delay-cntrl: up-clk, direct access + tx
2015-05-18 14:28:20 -04:00
2c1719095d
util_axis_resize: Changed _ip.tcl format to the standard format
2015-05-18 17:25:07 +03:00
c19749361d
Makefiles: Updated makefiles to have as a result the programming file instead of the project file.
...
Also fixed altera projects dependencies
2015-05-18 17:22:46 +03:00
672a5a4dfa
a10gx- updates
2015-05-14 14:35:43 -04:00
b311b9dac6
a10gx- updates
2015-05-14 14:35:42 -04:00
a07d11c3e9
axi_ad9361_tdd: Define control bits for continuous receive/transmit
2015-05-14 17:21:32 +03:00
c9c05e21c2
axi_dmac: Updated constraints to cover cases when the hierarchy is rebuilt by synthesis
2015-05-13 16:34:06 +03:00
7c9bc40c75
axi_ad9361&TDD: Update TDD
...
+ Delete unnecessary registers
+ Add the module ad_addsub.v to resolve additions and subtractions inside TDD control
+ Redefine the burst logic
+ Redesign the control signal generations
+ Note: This patch fix the TDD related timing violations
2015-05-13 14:03:01 +03:00
a1d680ee6b
ad9680- add hw tcl
2015-05-12 15:06:42 -04:00
833a3de6b5
ad9680- add hw tcl
2015-05-12 15:06:39 -04:00
48c769d431
ad9144- add hw tcl
2015-05-12 14:40:38 -04:00
553f89f59d
ad9144- add hw tcl
2015-05-12 14:39:57 -04:00
3226ca4374
fmcadc4- ad9680 version
2015-05-11 13:55:02 -04:00
c28ff2ff9a
fmcadc4- ad9680 version
2015-05-11 13:55:02 -04:00
Lars-Peter Clausen
Adrian Costina
Istvan Csomortani
Rejeesh Kutty
Istvan Csomortani