Rejeesh Kutty
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1d6ea64d04
|
up_gt: move status to up clock
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2014-12-16 08:48:13 -05:00 |
|
Rejeesh Kutty
|
16f64a75d6
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fifo2s: false path typo on source signals
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2014-12-15 13:00:13 -05:00 |
|
Rejeesh Kutty
|
04c10abc2f
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gth/gtx: share same cpll/qpll cpu settings
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2014-12-11 11:18:48 -05:00 |
Istvan Csomortani
|
19732d89fb
|
plddr3: Fix the adc_dwr pulse width
The adc_dwr signal pulse width was to long, need to be just one adc_clk cycle.
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2014-12-09 13:51:00 +02:00 |
Adrian Costina
|
6f8c259961
|
axi_hdmi_tx: Fixed typo in altera related core
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2014-12-09 09:56:14 +02:00 |
|
Adrian Costina
|
a70d27c094
|
axi_mc_speed: updated core to latest axi interface implementation
|
2014-12-05 11:53:11 +02:00 |
|
Adrian Costina
|
26f58914e2
|
axi_mc_current_monitor: updated core to latest axi interface implementation
|
2014-12-05 11:53:06 +02:00 |
|
Adrian Costina
|
7e8e1e4fd0
|
axi_mc_controller: updated core to latest axi interface implementation
|
2014-12-05 11:52:59 +02:00 |
Lars-Peter Clausen
|
8cc9adfc49
|
up_axi: Fix up_raddr/up_waddr port width
Make sure that the port declaration width matches with the reg declaration
later on.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
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2014-12-01 13:22:28 +01:00 |
|
Rejeesh Kutty
|
afddc45ba4
|
library/ccat: initial commit
|
2014-11-25 12:59:51 -05:00 |
|
Rejeesh Kutty
|
196e8b119c
|
library/bsplit: initial commit
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2014-11-25 12:59:50 -05:00 |
|
Rejeesh Kutty
|
403f8c0631
|
util_cpack: ipi doesn't like local params
|
2014-11-21 15:32:13 -05:00 |
|
Rejeesh Kutty
|
3b500bafcc
|
util_cpack: add port controls on ipi
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2014-11-21 15:32:12 -05:00 |
|
Rejeesh Kutty
|
5ca2944b70
|
library/util_cpack: initial checkin
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2014-11-21 15:32:10 -05:00 |
|
Istvan Csomortani
|
42874bfe81
|
prcfg_library: Major update
Get rid of the QPSK symbol wrapper for now. The DMA data path is using the 2 LSB bits.
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2014-11-18 10:05:52 +02:00 |
|
Rejeesh Kutty
|
a4724f8396
|
es: added kcu105 gth
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2014-11-17 09:55:12 -05:00 |
|
Rejeesh Kutty
|
b1c91fac92
|
es: added kcu105 gth
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2014-11-17 09:55:10 -05:00 |
|
Rejeesh Kutty
|
fd305f2eff
|
es: added kcu105 gth
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2014-11-17 09:55:09 -05:00 |
|
Adrian Costina
|
6dd1226696
|
axi_ad9643: Fixed constraint file
|
2014-11-17 12:12:09 +02:00 |
|
Adrian Costina
|
8831d9dbd7
|
axi_ad9122: fixed constraint file
|
2014-11-17 12:11:20 +02:00 |
|
Adrian Costina
|
2744d0cb37
|
util_wfifo: Update to implement flip flops
|
2014-11-17 12:10:21 +02:00 |
|
Rejeesh Kutty
|
41ffc66c26
|
fifo2s: removed m interface
|
2014-11-13 15:00:03 -05:00 |
|
Rejeesh Kutty
|
8761db438e
|
axi_fifo2f: common interface with fifo2s
|
2014-11-12 15:15:32 -05:00 |
|
Rejeesh Kutty
|
925e966eb6
|
axi_fifo2s: fifo full replaced with ready
|
2014-11-12 14:43:47 -05:00 |
|
Rejeesh Kutty
|
5fc4f1b000
|
axi_fifo2s: buswidth fix
|
2014-11-12 14:43:46 -05:00 |
|
Rejeesh Kutty
|
d204a7c2b7
|
axi_fifo2s: include bus width/clock transfer
|
2014-11-12 14:43:44 -05:00 |
|
Rejeesh Kutty
|
e7cec7171e
|
axi_fifo2s: include bus width/clock transfer
|
2014-11-12 14:43:43 -05:00 |
|
Rejeesh Kutty
|
4381f20a6a
|
axi_fifo2s: include bus width/clock transfer
|
2014-11-12 14:43:42 -05:00 |
|
Rejeesh Kutty
|
9f2dbad539
|
axi_fifo2s: include bus width/clock transfer
|
2014-11-12 14:43:41 -05:00 |
|
Rejeesh Kutty
|
e683b5868e
|
axi_fifo2s: include bus width/clock transfer
|
2014-11-12 14:43:40 -05:00 |
|
Rejeesh Kutty
|
81b4cd532d
|
axi_fifo2s: include bus width/clock transfer
|
2014-11-12 14:43:38 -05:00 |
|
Rejeesh Kutty
|
888ab888d2
|
axi_fifo2s: include bus width/clock transfer
|
2014-11-12 14:43:37 -05:00 |
|
Istvan Csomortani
|
f8e7796592
|
axi_jesd_gt: Fix lane number parameters
|
2014-11-12 17:43:32 +02:00 |
|
Istvan Csomortani
|
bf62665c56
|
prcfg_qpsk: Add Simulink model
Matlab version used: R2014a, HDL Coder 3.3
|
2014-11-12 15:44:38 +02:00 |
|
Rejeesh Kutty
|
64ec633438
|
gt: asymmetric no of lanes
|
2014-11-11 08:54:24 -05:00 |
|
Rejeesh Kutty
|
cb15567a56
|
ad6676: added
|
2014-11-10 13:36:07 -05:00 |
|
Istvan Csomortani
|
c6df568a00
|
Revert "ad_interrupts: Initial check in."
This reverts commit b254380338.
|
2014-11-06 12:16:52 +02:00 |
|
Rejeesh Kutty
|
b11d80ed98
|
ad_rst: changed to dual stage
|
2014-11-05 16:48:02 -05:00 |
|
Rejeesh Kutty
|
74ec396b27
|
ad_rst: ultrascale -dual stage
|
2014-11-05 16:47:41 -05:00 |
|
Rejeesh Kutty
|
d69ccebbde
|
ad9234: full 16bit samples
|
2014-11-05 11:59:08 -05:00 |
|
Rejeesh Kutty
|
403fe1b373
|
wfifo: read only if ready is asserted
|
2014-10-31 13:05:17 -04:00 |
|
Adrian Costina
|
38652b1c3e
|
axi_ad9643: Added constraint file
|
2014-10-31 17:57:47 +02:00 |
|
Adrian Costina
|
3e9ce71d21
|
axi_ad9122: Added constraint file
|
2014-10-31 17:56:56 +02:00 |
|
Istvan Csomortani
|
d596d71285
|
prcfg_qpsk: Swap the I/Q pair nets between the filter and the demodulator.
This fix the wrong symbol mapping issue.
|
2014-10-31 12:14:52 +02:00 |
|
Istvan Csomortani
|
eb520b1f75
|
prcfg_qpsk: Major update
Add a symbol wrapper to the logic. Wraps the 32 bit data to 2 bit symbols.
|
2014-10-31 12:10:59 +02:00 |
|
Istvan Csomortani
|
ea194755e1
|
prcfg: Upgrade the QPSK logic
Regenerate the qpsk logic, with the new HDL coder, and modify the design to support the new files.
|
2014-10-31 11:59:29 +02:00 |
|
Rejeesh Kutty
|
9818bcb601
|
axi_fifo2f: internal memory low overhead
|
2014-10-30 11:12:10 -04:00 |
|
Rejeesh Kutty
|
17cb1d9585
|
common/mem: asymmetric version
|
2014-10-30 11:12:09 -04:00 |
|
Rejeesh Kutty
|
6470ea91ad
|
axi_fifo2f: fake version
|
2014-10-30 11:12:08 -04:00 |
|
Lars-Peter Clausen
|
f9628262aa
|
axi_dmac: Add xfer_req signal to the streamin AXI source interface
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
|
2014-10-29 18:15:54 +01:00 |