Commit Graph

265 Commits (4ce153e6e15aa4202a39a868c5120c73c516760f)

Author SHA1 Message Date
Laszlo Nagy db25ee1877 axi_dmac: fix transfer start synchronization
This change will fix the transfer start synchronization mechanism used
in the AXIS streaming and FIFO source interfaces.
2018-09-11 17:01:58 +03:00
Laszlo Nagy 9d6f3de448 axi_dmac: assert xfer_request only when ready
If the req_valid asserts faster than the ID gets synchronized over we
assert the xfer request without being ready to accept data.
This can lead to overflow assertion when using a FIFO like interface.
2018-09-07 11:38:04 +03:00
Laszlo Nagy 20ac7dcaef axi_dmac: component level testbench updates 2018-09-07 11:38:04 +03:00
Laszlo Nagy a4c4e384bb axi_dmac: early abort 2d support 2018-09-07 11:38:04 +03:00
Laszlo Nagy a1cc20e3b9 axi_dmac: early abort support
Data mover/ src axis changes
  Request rewind ID if TLAST received during non-last burst
  Consume (ignore) descriptors until last segment received
  Block descriptors towards destination until last segment received

Request generator changes
  Rewind the burst ID if rewind request received
  Consume (ignore) descriptors until last segment received
  If TLAST happened on last segment replay next transfer (in progress or
   completed) with the adjusted ID
  Create completion requests for ignored segments

Response generator changes
  Track requests
  Complete segments which got ignored
2018-09-07 11:38:04 +03:00
Laszlo Nagy 2f3a95971c axi_dmac: request generator reworked to use FSM 2018-09-07 11:38:04 +03:00
Laszlo Nagy eb40b42c88 axi_dmac: preparation work for reporting length of partial transfers
Length of partial transfers are stored in a queue for SW reads.
The presence of partial transfer is indicated by a status bit.

The reporting can be enabled by a control bit.

The progress of any transfer can be followed by a debug register.
2018-09-07 11:38:04 +03:00
Laszlo Nagy 0203cd6981 axi_dmac: drive destination eot from source side 2018-09-07 11:38:04 +03:00
Laszlo Nagy 681b619fff axi_dmac: wire destination descriptor through source
Drive the descriptor from the source side to destination
so we can abort consecutive transfers in case TLAST asserts.

For AXIS count the length of the burst and pass that value to the
destination instead the programmed one. This is useful when the
streams aborts early by asserting the TLAST. We want to notify the
destination with the right number of beats received.

For FIFO source interface reuse the same logic due the small footprint
even if the stream does not got interrupted in that case.
For MM source interface wire the burst length from the request side to
destination.
2018-09-07 11:38:04 +03:00
Laszlo Nagy ef4ceac6fc axi_dmac: Reduce the width of ID signals to minimum
Reduce the width of ID signals to avoid size mismatches in Arria 10 SoC
projects where the ID width of the hard IP is 4.
The width of ID that reaches the slave can be increased by the interconnect if
multiple masters access the slave so we end up with mismatches.

Since these signals are unused it is safe to reduce them to minimum width and
let the interconnect zero-extend them as required.
2018-08-21 14:08:14 +03:00
Laszlo Nagy cff06bd779 axi_dmac: Use AXI3 for DMAC in Intel projects
The buffers inside the interconnect are sized based on maximum burst sizes
the masters can produce.
For AXI4 the max burst size is 128 but for these projects for the
default burst size of 128 bytes the DMACs are creating only burst of 8 or
16 beats depending on the bus width (128bits and 64 bits respectively).

These burst sizes can fit in the AXI3 protocol where the max burst
length is 16. Therefore the interconnect will be reduced.

The observed reduction is around 4 Mb of block RAM per project.
Another benefit is a better timing closure,
since these buffers reside in the DDR3 clock domain.
2018-08-21 14:08:14 +03:00
Laszlo Nagy 4d8008e64c axi_dmac: fix address width detection
The round function from tcl is a rounding to nearest. Using it in address
width calculation produces incorrect values.
e.g.
 round(log(0xAF000000)/log(2)) will produce 31 instead of 32

The fix is to replace the rounding function with ceiling that guarantees
rounding up.
2018-07-20 18:12:24 +03:00
Laszlo Nagy e79992f9c5 axi_dmac: TLAST support for 2d transfers
In MM2S applications like video DMA it is useful to mark the end of the stream
with the TLAST.
The change enables the generation of the TLAST on the last beat of the
last row of the 2d transfer.
2018-07-13 13:46:40 +03:00
Laszlo Nagy c5b62a04b7 axi_dmac: fix 2d transfer address width
The index on MSB of addresses was set to 31,
but the width of address in the axi_dmac depends on a parameter.
The mismatch causes issues in the Xilinx simulator which does not extends the
narrower width signal with zeros, instead the wider signal gets 'Z' on its MSBs.
When the address was incremented with the stride it became 'X' due the uninitialized
MSBs.
2018-07-12 16:53:06 +03:00
Laszlo Nagy e794d04cd1 axi_dmac: renamed .h files to .vh
Vivado recognises .h files as C header files,
the expected extension for Verilog Header is .vh
This causes issues in simulating block designs  since these files
won't be exported for the simulation even if they are
part of the simulation fileset.
2018-07-11 11:30:22 +03:00
Laszlo Nagy 7713738d12 axi_dmac: ttcl file support for simulation
When creating a block design targeted for simulation, in the testbench
it is useful to know the parameters of the sub components (e.g DMAC)
Xilinx's way to pass the parameters to the testbench in case of it's AXI
verification IP is through package files. We will do the same for the DMAC.

The package file can be generated from template files (ttcl).
These will be added only to the simulation file set of the project and
won't affect synthesis.
2018-07-11 11:30:22 +03:00
Laszlo Nagy 0d0989da39 axi_dmac: diagnostic interface in bursts
This change adds a diagnostic interface to the DMAC core.
The interface exposes internal information about the core,
information which can't be exposed through AXI registers
due the latency and update rate.

Such information is the fullness of the internal buffer.
For this is exposed in bursts and is driven from the destination
clock domain, as this is reflected in its name.

The signal has a fixed size and is dimensioned by
taking in account the supported maximum number of bursts of 128.
2018-07-10 12:30:34 +03:00
Laszlo Nagy 7f4b6caa81 axi_dmac: Remove unused constraint
The constraint referred to registers which got renamed,
causing critical warnings.
2018-07-06 16:31:40 +03:00
Laszlo Nagy e2c75c015f axi_dmac: add tlast to the axis interface for Intel
This change adds the TLAST signal to the AXI streaming interface
of the source side for Intel targets.
Xilinx based designs already have this since the tlast is part of the
interface definition.

In order to make the signal optional and let the tool connect a
default value to the it, the USE_TLAST_SRC/DEST parameter is
added to the configuration UI. This conditions the tlast port on
the interface of the DMAC.

Xilinx handles the optional signals much better so the parameter
is not required there.
2018-07-06 16:30:30 +03:00
Lars-Peter Clausen 8ddcffcafc axi_dmac: Enforce transfer length and stride alignments
In its current implementation the DMAC requires that the length of a
transfer is aligned to the widest interface. E.g. if the widest interface
is 128 bits wide the length of the transfer needs to be a multiple of 16
bytes.

If the requested length is not aligned to the interface width it will be
rounded up.

This works fine as long as both interfaces have the same width. If they
have different widths it is possible that the length is rounded up to
different values on the source and destination side. In that case the DMA
will deadlock because the transfer lengths don't match and either not enough
of too much data is delivered from the source to the destination side.

Currently it is up to software to make sure that such an invalid
configuration is not possible.

Also enforce this requirement in the DMAC itself by setting the LSBs of the
transfer length to a fixed 1 so that the length is always aligned to the
widest interface.

Software can also use this to discover the length alignment requirement, by
first writing a zero to the length register and then reading the register
back. The LSBs of the read back value will be non-zero indicating the
alignment requirement.

In a similar way the stride needs to be aligned to the width of its
respective interface, so the generated addresses stay aligned. Enforce this
in the same way by keeping the LSBs cleared.

Increment the minor version number to reflect these changes.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-07-03 13:44:34 +02:00
Lars-Peter Clausen c4cb3dfb37 axi_dmac: Move transfer abort logic to data mover
The transfer abort logic in the src_axi_stream module is making some
assumptions about the internal timings of the data mover module.

Move this logic inside the data mover module. This will make it easier to
update the internal logic without having to update other modules.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-07-03 13:44:34 +02:00
Lars-Peter Clausen 92984dc802 axi_dmac: Move sync transfer start logic to the data mover
The only two users of the data mover module both implement the same
sync-transfer-start logic. Move this into the data mover module to avoid
the duplicated code.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-07-03 13:44:34 +02:00
Lars-Peter Clausen 62969bd7ab axi_dmac: Cleanup data mover
With the recent rework there is now a fair amount of dead code in the
datamover module that is no longer used. Remove it.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-07-03 13:44:34 +02:00
Lars-Peter Clausen 44e09f58cd axi_dmac: Remove backpressure from the source pipeline
Data is gated on the source side interface and not let into the pipeline if
there is no space available inside the store and forward memory.

This means whenever data is let into the pipeline space is available and
backpressure wont be asserted. Remove the backpressure signals altogether
to simplify the design.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-07-03 13:44:34 +02:00
Lars-Peter Clausen 7d643e216a axi_dmac: Limit number of bursts on the source side
Currently the source side of the DMAC can issue requests for up to
2*FIFO_SIZE-1 bursts even though there is only room for FIFO_SIZE bursts in
the store and forward memory.

This can problematic for memory mapped buses. If the data is not read fast
enough from the DMAC back-pressure will propagate through the whole system
memory subsystem and can cause significant performance penalty or even a
deadlock halting the whole system.

To avoid this make sure that not more that than what fits into the
store-and-forward memory is requested by throttling the request ID based
on how much room is available in the memory.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-07-03 13:44:34 +02:00
Lars-Peter Clausen d80175d895 axi_dmac: Remove second destination side register slice
The second destination side register slice was put in place to provide
additional slack on some of the datapath control signals. It looks as if
this is no longer required for the latest version of the DMA controller.
All timing paths have sufficient margin.

So remove this extra slice register which just takes up resources and adds
pipeline latency.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-07-03 13:44:34 +02:00
Lars-Peter Clausen 0d337edbdf axi_dmac: Eliminate beat counter for the destination interfaces
Currently both the source side and the destination side interfaces employ a
beat counter to identify the last beat in a burst.

The burst memory already has an internal last signal on the destination
side. Exporting it allows the destination side interfaces to use it instead
of having to generate their own signal. This allows to eliminate the beat
counters on the destination side and simplify the data path logic.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-07-03 13:44:34 +02:00
Lars-Peter Clausen 71e14f64e6 axi_dmac: Route destination request ID through the burst memory
Currently the destination side request ID is synchronized response ID from
the source side. This signal is effectively the same as the synchronized
src ID inside the burst memory. The only difference is that they might not
increment in the exact same clock cycle.

Exporting the request ID from the burst memory means we can remove the extra
synchronizer block.

This has the added bonus that the request ID will increment in the same
clock cycle as when the data becomes available from the memory.

This means we can assume that when there is a outstanding burst request
indicated via the ID that data is available from the memory and vice versa
when data is available from the memory that there is a outstanding burst
request.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-07-03 13:44:34 +02:00
Lars-Peter Clausen 859e3d2ed1 axi_dmac: Rework data store-and-forward buffer
Currently the DMAC uses a simple FIFO as the store-and-forward buffer. The
FIFO handshaking is beat based whereas the remainder of the DMAC is burst
based. This means that additional control signals have to be combined with
the FIFO handshaking signal to generate the external handshaking signals.

Re-work the store-and-forward buffer to utilize a BRAM that is subdivided
into N segments. Where N is the maximum number of bursts that can be stored
in the buffer and each segment has the size of the maximum burst length.
Each segment stores the data associated with one burst and even when the
burst is shorter than the maximum burst length the next burst will be
stored in the next segment.

The new store-and-forward buffer takes care of generating all the
handshaking signals. This means handshaking is generated in a central place
and does not have to be combined from multiple data-paths simplifying the
overall logic.

The new store-and-forward buffer also takes care of data width up- and
down-sizing in case that the source and sink modules have a different data
width. This tighter integration will allow future enhancements like using
asymmetric memory.

This re-work lays the foundation of future enhancements to the DMA like
support for un-aligned transfers and early transfer abort which would have
been much more difficult to implement with the previous architecture.

In addition it significantly reduces the resource utilization of the
store-and-forward buffer and allows for better timing due to reduced
combinatorial path lengths.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-07-03 13:44:34 +02:00
Lars-Peter Clausen fa99afcf94 axi_dmac: dest_axi_mm: Simplify dependency management
There is an implicit dependency between the outgoing data stream and the
incoming response stream. The AXI specification requires that the
corresponding response is not sent before the last beat of data has been
received.

We can take advantage of this and remove the currently explicit dependency
between the data and response paths. This slightly simplifies the design.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-07-03 13:44:34 +02:00
Lars-Peter Clausen 8c1d8e20da axi_dmac: Allow to disable FIFO interfaces immediately
For the AXI streaming interfaces we need to make sure that the handshaking
rules for the external interface are met. Hence we can't just disable the
DMA and have to wait for any pending beats to complete.

For the FIFO interfaces on the other hand no such requirements exist. All
handshaking is for the internal pipeline which will be reset as a whole so
it is OK to violate the handshaking without causing any undefined behavior.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-07-03 13:44:34 +02:00
Lars-Peter Clausen 8937c365a0 axi_dmac: Hook up rlast for MM-AXI source interface
For the memory-mapped AXI read interface the slave asserts rlast for the
last beat in a burst.

This means we don't have to count the number of beats to know when the
burst is completed but instead can use rlast. This slightly reduces the
amount of resources needed for the MM-AXI source module and given that the
beat_counter is often the bottleneck timing wise this should also improve
the timing.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-07-03 13:44:34 +02:00
Lars-Peter Clausen 8b272cfeba axi_dmac: Add testbenches that exercise DMA shutdown
When the DMA is disabled it should gracefully shutdown and eventually end
up in an idle state. All outstanding AXI MM requests need to complete
before the DMA is fully disabled.

Add testbenches that test this for both AXI MM read and write behavior.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-07-03 13:44:34 +02:00
Lars-Peter Clausen 02bc91ad3a axi_dmac: Rework transfer shutdown
The DMAC allows a transfer to be aborted. When a transfer is aborted the
DMAC shuts down as fast as possible while still completing any pending
transactions as required by the protocol specifications of the port. E.g.
for AXI-MM this means to complete all outstanding bursts.

Once the DMAC has entered an idle state a special synchronization signal is
send to all modules. This synchronization signal instructs them to flush
the pipeline and remove any stale data and metadata associated with the
aborted transfer. Once all data has been flushed the DMAC enters the
shutdown state and is ready for the next transfer.

In addition each module has a reset that resets the modules state and is
used at system startup to bring them into a consistent state.

Re-work the shutdown process to instead of flushing the pipeline re-use the
startup reset signal also for shutdown.

To manage the reset signal generation introduce the reset manager module.
It contains a state machine that will assert the reset signals in the
correct order and for the appropriate duration in case of a transfer
shutdown.

The reset signal is asserted in all domains until it has been asserted for
at least 4 clock cycles in the slowest domain. This ensures that the reset
signal is not de-asserted in the faster domains before the slower domains
have had a chance to process the reset signal.

In addition the reset signal is de-asserted in the opposite direction of
the data flow. This ensures that the data sink is ready to receive data
before the data source can start sending data. This simplifies the internal
handshaking.

This approach has multiple advantages.
 * Issuing a reset and removing all state takes less time than
   explicitly flushing one sample per clock cycle at a time.
 * It simplifies the logic in the faster clock domains at the expense of
   more complicated logic in the slower control clock domain. This allows
   for higher fMax on the data paths.
 * Less signals to synchronize from the control domain to the data domains

The implementation of the pause mode has also slightly changed. Pause is
now a simple disable of the data domains. When the transfer is resumed
after a pause the data domains are re-enabled and continue at their
previous state.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-07-03 13:44:34 +02:00
Lars-Peter Clausen 95c98c634e axi_dmac: Split transfer handling into separate sub-module
Move the transfer logic, including the 2d module, into its own sub-module.
This allows testing of the full transfer logic independently of the
register map logic.

The top-level module now only instantiates the register map and transfer
module, but does not have any logic on its own.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-07-03 13:44:34 +02:00
Lars-Peter Clausen 80cfe2675d axi_dmac: Be more specific about debug register timing exceptions
The timing exceptions for the debug paths are currently a bit to broad and
can include paths that should not have an exception.

All the debug signals are coming from the i_request_arb instance, so
include that in the match to avoid false positives.

For most projects this wont have been a problem since there is usually a
fair amount of slack on the paths that were affected by this. But in
projects with high utilization this might result in undefined behavior.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-06-13 10:12:22 +02:00
Lars-Peter Clausen 80e7ba56a8 axi_dmac: Revert EOT memory to FIFO structure
This reverts commit 4b1d9fc86b "axi_dmac: Modified in order to avoid
vivado crash".

Vivado no longer crashes and this structure is much more efficient when it
comes to resource usage and timing. The intention here is to create a 1-bit
memory that is N entries deep and not a N bit signal.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-06-05 14:28:40 +02:00
Lars-Peter Clausen 8b8df70df1 axi_dmac: request_generator: Remove reset from data path
The burst_count signal and its derived signals are not used until the
burst_count has been explicitly initialized by loading a transfer. There is
no need to have a reset.

This reduces the fan-out of the reset signal.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-06-05 14:28:40 +02:00
Lars-Peter Clausen 6bc1eae48d axi_dmac: 2d_transfer: Remove resets from data path
The data path register of the 2d_transfer module are qualified by the
corresponding valid signal. Their content is not used until they have been
explicitly initialized. There is no need to reset them explicitly.

This reduces the fan-out of the reset signal.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-06-05 14:28:40 +02:00
Lars-Peter Clausen 6b7a46410c axi_dmac: address_generator: Remove resets from data path
There is no need to reset the data path in the address generator. The
values of the register on the data path are not used until they have been
explicitly initialized. Removing the reset simplifies the structure and
reduces the fan-out of the reset signal.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-06-05 14:28:40 +02:00
Lars-Peter Clausen 67600f9831 axi_dmac: Use localparam instead of parameter
Xilinx tools don't allow to use $clog2() when computing the value of a
localparam, even though it is valid Verilog.

For this reason a parameter was used for BYTES_PER_BURST_WIDTH so far. But
that generates warnings from both Quartus and Vivado since the parameter is
not part of the parameter list.

Fix this by changing it to a localparam and computing the log2() manually.
The upper limit for the burst length is known to be 4k, so values larger
than that don't have to be supported.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-06-05 14:28:40 +02:00
Lars-Peter Clausen cf5208122a axi_dmac: Increase default store-and-forward memory size to 8 bursts
A larger store-and-forward memory provides better protection against worst
case memory interface latencies by being able to store more data before
over-/underflowing.

Based on empirical testing it was found that using a size of 4 bursts can
still result in underflows/overflows under certain conditions. These do not
happen when using a size of 8 bursts.

This change does not significantly increase resource consumption. Both on
Intel and Xilinx the block RAM has a minimum depth of 512 entries. With a
default burst length of 16 beats that allows for up to 32 bursts without
requiring additional block RAM.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-06-05 14:28:40 +02:00
Lars-Peter Clausen b18b16fd3a axi_dmac: Use a more descriptive label for the store-and-forward memory size
The label for the store-and-forward memory size configuration option at the
moment is just "FIFO Size" and while the store-and-forward memory uses a
FIFO that is just a implementation detail.

Change the label to "Store-and-Forward Memory Size". This is more
descriptive as it references the function not the implementation.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-06-05 14:28:40 +02:00
Lars-Peter Clausen 15b0e38e23 axi_dmac: List valid store-and-forward memory sizes
For correct operation the store-and-forward memory size must be a
power-of-two in the range of 2 to 32.

This is simple enough so we can list all values and let the IP Integrator
and QSYS perform proper validation of the parameter.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-06-05 14:28:40 +02:00
Lars-Peter Clausen 682895c7ae axi_dmac: dest_axi_stream: Remove outdated comment
This comment hasn't been true in a long long time. It does not have any
relation to the code around it anymore.

So just remove it.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-06-05 14:28:40 +02:00
Lars-Peter Clausen 7a804c1d76 axi_dmac: Fix debug ID order
Commit e6aacd2f56 ("axi_dmac: Better support debug IDs when ID_WIDTH !=
3") managed to get the order of the IDs in the debug register wrong.
Restore the original order.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-05-04 12:40:15 +02:00
Laszlo Nagy 3f94fec620 axi_dmac/dma_write_tb: added data integrity check
Added passing condition checking.
Added variable request sizes
2018-05-03 14:49:06 +02:00
Laszlo Nagy 5c2e10eca5 axi_dmac: added ModelSim support to run_tb.sh
Modified run_tb.sh to work with Modelsim if the SIMULATOR variable is set to
"modelsim"
2018-05-03 14:49:06 +02:00
Laszlo Nagy ee4932ecee axi_dmac: made vlog pass
Did minor changes to the code to make ModelSim vlog pass.
2018-05-03 14:49:06 +02:00
Lars-Peter Clausen 24d17e8bcc axi_dmac: Add transfer testbenches
Add simple transfer testbenches that test the read and write to AXI memory
paths of the DMAC.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-05-03 14:49:06 +02:00