Rejeesh Kutty
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debbe31713
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Merge remote-tracking branch 'origin/master' into dev
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2015-01-09 11:12:56 -05:00 |
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Rejeesh Kutty
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63633a0fa5
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ad9739a: constraints
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2015-01-08 10:25:45 -05:00 |
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Rejeesh Kutty
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ed73a9d1cf
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ad9739a: updated to ad9739a
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2015-01-08 10:25:15 -05:00 |
Istvan Csomortani
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14df46c193
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library: Initial commit of axi_hdmi_rx ip core
Status unknown, NOT tested.
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2015-01-08 16:58:56 +02:00 |
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Istvan Csomortani
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9f485f2f4e
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common: Add register map module for HDMI receiver.
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2015-01-08 12:24:47 +02:00 |
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Istvan Csomortani
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161e6cc70d
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common: Add color space sampling and color space conversion modules
This two module are used by the HDMI receiver.
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2015-01-08 12:24:46 +02:00 |
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Rejeesh Kutty
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ad4b4f64d0
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ad9739a: ad9122 copy
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2015-01-07 15:36:02 -05:00 |
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Rejeesh Kutty
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3a4d765a2b
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up_clkgen: reading typo
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2015-01-07 14:02:39 -05:00 |
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Rejeesh Kutty
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b65bcab8d6
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up_clkgen: reading typo
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2015-01-07 13:58:43 -05:00 |
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Rejeesh Kutty
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5f93c859b5
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util_rfifo: renamed ports to make vivado happy
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2015-01-06 16:16:42 -05:00 |
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Rejeesh Kutty
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8056574bae
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util_wfifo: renamed ports to make vivado happy
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2015-01-06 16:16:25 -05:00 |
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Rejeesh Kutty
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0291bb3bf7
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util_rfifo: port name fixes & doc.
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2015-01-06 16:15:51 -05:00 |
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Rejeesh Kutty
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36b041ccc0
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util_wfifo: port name fixes & doc.
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2015-01-06 16:15:42 -05:00 |
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Rejeesh Kutty
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ee0912eb6a
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ad9361: make 2t2r external for mw
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2015-01-05 10:54:23 -05:00 |
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Rejeesh Kutty
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c3529f112f
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up_gt: move status to up clock
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2014-12-19 13:00:27 +02:00 |
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Rejeesh Kutty
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f4774d6f98
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fifo2s: false path typo on source signals
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2014-12-19 13:00:13 +02:00 |
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Rejeesh Kutty
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1d6ea64d04
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up_gt: move status to up clock
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2014-12-16 08:48:13 -05:00 |
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Rejeesh Kutty
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16f64a75d6
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fifo2s: false path typo on source signals
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2014-12-15 13:00:13 -05:00 |
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Rejeesh Kutty
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04c10abc2f
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gth/gtx: share same cpll/qpll cpu settings
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2014-12-11 11:18:48 -05:00 |
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Istvan Csomortani
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c4152627f0
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plddr3: Sync adc_wcnt_int to adc_wr and fix adc_dwr pulse width
The adc_wcnt_int must be synchronized to adc_wr. The adc_dwr signal pulse width was to long,
it needs to be just one adc_clk cycle.
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2014-12-09 13:59:19 +02:00 |
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Istvan Csomortani
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19732d89fb
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plddr3: Fix the adc_dwr pulse width
The adc_dwr signal pulse width was to long, need to be just one adc_clk cycle.
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2014-12-09 13:51:00 +02:00 |
Adrian Costina
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6aad2fbbb2
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axi_hdmi_tx: Fixed typo in altera related core
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2014-12-09 10:19:03 +02:00 |
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Adrian Costina
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6f8c259961
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axi_hdmi_tx: Fixed typo in altera related core
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2014-12-09 09:56:14 +02:00 |
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Adrian Costina
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a70d27c094
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axi_mc_speed: updated core to latest axi interface implementation
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2014-12-05 11:53:11 +02:00 |
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Adrian Costina
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26f58914e2
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axi_mc_current_monitor: updated core to latest axi interface implementation
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2014-12-05 11:53:06 +02:00 |
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Adrian Costina
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7e8e1e4fd0
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axi_mc_controller: updated core to latest axi interface implementation
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2014-12-05 11:52:59 +02:00 |
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Adrian Costina
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ea1a50c985
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axi_mc_speed: updated core to latest axi interface implementation
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2014-12-05 11:46:20 +02:00 |
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Adrian Costina
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0d2888a5a6
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axi_mc_current_monitor: updated core to latest axi interface implementation
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2014-12-05 11:45:37 +02:00 |
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Adrian Costina
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21591dc485
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axi_mc_controller: updated core to latest axi interface implementation
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2014-12-05 11:43:59 +02:00 |
Lars-Peter Clausen
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6197563506
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up_axi: Fix up_raddr/up_waddr port width
Make sure that the port declaration width matches with the reg declaration
later on.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
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2014-12-01 13:45:45 +01:00 |
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Lars-Peter Clausen
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8cc9adfc49
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up_axi: Fix up_raddr/up_waddr port width
Make sure that the port declaration width matches with the reg declaration
later on.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
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2014-12-01 13:22:28 +01:00 |
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Rejeesh Kutty
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afddc45ba4
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library/ccat: initial commit
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2014-11-25 12:59:51 -05:00 |
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Rejeesh Kutty
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196e8b119c
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library/bsplit: initial commit
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2014-11-25 12:59:50 -05:00 |
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Rejeesh Kutty
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403f8c0631
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util_cpack: ipi doesn't like local params
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2014-11-21 15:32:13 -05:00 |
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Rejeesh Kutty
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3b500bafcc
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util_cpack: add port controls on ipi
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2014-11-21 15:32:12 -05:00 |
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Rejeesh Kutty
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5ca2944b70
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library/util_cpack: initial checkin
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2014-11-21 15:32:10 -05:00 |
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Istvan Csomortani
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42874bfe81
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prcfg_library: Major update
Get rid of the QPSK symbol wrapper for now. The DMA data path is using the 2 LSB bits.
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2014-11-18 10:05:52 +02:00 |
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Rejeesh Kutty
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a4724f8396
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es: added kcu105 gth
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2014-11-17 09:55:12 -05:00 |
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Rejeesh Kutty
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b1c91fac92
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es: added kcu105 gth
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2014-11-17 09:55:10 -05:00 |
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Rejeesh Kutty
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fd305f2eff
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es: added kcu105 gth
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2014-11-17 09:55:09 -05:00 |
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Adrian Costina
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6dd1226696
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axi_ad9643: Fixed constraint file
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2014-11-17 12:12:09 +02:00 |
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Adrian Costina
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8831d9dbd7
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axi_ad9122: fixed constraint file
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2014-11-17 12:11:20 +02:00 |
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Adrian Costina
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2744d0cb37
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util_wfifo: Update to implement flip flops
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2014-11-17 12:10:21 +02:00 |
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Rejeesh Kutty
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41ffc66c26
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fifo2s: removed m interface
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2014-11-13 15:00:03 -05:00 |
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Rejeesh Kutty
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8761db438e
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axi_fifo2f: common interface with fifo2s
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2014-11-12 15:15:32 -05:00 |
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Rejeesh Kutty
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925e966eb6
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axi_fifo2s: fifo full replaced with ready
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2014-11-12 14:43:47 -05:00 |
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Rejeesh Kutty
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5fc4f1b000
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axi_fifo2s: buswidth fix
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2014-11-12 14:43:46 -05:00 |
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Rejeesh Kutty
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d204a7c2b7
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axi_fifo2s: include bus width/clock transfer
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2014-11-12 14:43:44 -05:00 |
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Rejeesh Kutty
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e7cec7171e
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axi_fifo2s: include bus width/clock transfer
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2014-11-12 14:43:43 -05:00 |
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Rejeesh Kutty
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4381f20a6a
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axi_fifo2s: include bus width/clock transfer
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2014-11-12 14:43:42 -05:00 |