* Removed the commercial JESD license and put the ADIBSD or GPL v2 like
for other Verilog files
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
* Added header license for the files that didn't have
* Modified parentheses
* Removed extra spaces at the end of lines
* Fixed parameters list to be each parameter on its line
* Deleted lines after endmodule and consecutive empty lines
* Fixed indentation
Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
Build a large mux from smaller ones defined by the REQ_MUX_SZ parameter
Use EN_REG to add a register at the output of the small muxes to help
timing closure.
Iulia Moldovan
Laszlo Nagy