The SPI Engine cores were named directly inside the script and this
would mean that for multiple SPI Engine instances IPs with the same
name would appear. These updates will introduce the hierarchy name
into the name given to the cores and will therefore allow for
multiple instances of SPI Engine to be added to the same Xilinx
project.
Projects which use spi_engine.tcl will be updated to account for
these changes.
* Added header license for the files that didn't have
* Modified parentheses
* Removed extra spaces at the end of lines
* Fixed parameters list to be each parameter on its line
* Deleted lines after endmodule and consecutive empty lines
* Fixed indentation
Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
The 4 parameters are added to facilitate transmiting project
related information to the software. They act as read-only
memory which is written in Vivado when the project builds.
Set 31 to SDI FIFO's almost full threshold
In case of multiple SDI (MISO) lanes, the samples arrives in a parallel
fashion. For example in case of 4 MISO line, at the first latching clock
edge 4 bits of a sample will be saved, one bit into each shift register.
The data reorder module reconstruct the incoming samples from the AXI
stream of the offload module.
There are boards (e.g. AD4630-24) which take the SCLK and echo back to
the FPGA through a level shifter - doing this removes the effect of
round-trip timing delays from the level shifter. This is commonly done
whenever isolators are used since they are very slow.
By setting the ECHO_SCLK parameter to 1, the IP will use the incoming
echoed SCLK clock to latch the SDI line(s). The sdi_data_valid is still
synchronous to the SPI clock, and it's generated after the last valid
SDI latch.
The designer's responsibility is to time the SDI shift registers in order to
respect the design requirements.
This reverts commit 0402ce85e4
and reverts commit 164aa97ec3.
The trigger pulse generation must be handled outside of the
SPI Engine framework.
It is recommanded to be done in system level using a PWM
generator or an external signal.
Define both AXI4 Memory Mapped and microprocessor interface for the
reigster map, then activate/deactive one of it in fucntion of the memory
interface type parameter.
Define the missing status_sync interface, which should be connected to
the offload.
Context switching with a parameter is not a good idea. The simulator
may evaluate both branch of the IF statement, even though the inactive
branch may not be valid.
Use if..generate to make the code more robust for both synthesizers and
simulators.
Fix the *_ip.tcl scripts for axi_spi_engine and spi_engine_offload
module.
In case of a bool parameters the value_format and value properties must
be set for both user and hdl paramters. If not, in the generated verilog
code the tool will use "true" or "false" strings, instead of 0 or 1.
The sdo_enabled and sdi_enabled control lines are generated from the
current state of the CMD bus.
In case of a delayed SDI latching the sdi_enabled can be deasserted at
the moment of the last valid bit, losing the generation of the sdi_data_valid
signal, which eventually cause a data loss, or even deadlock on software driver.
To make the logic mode robust, latch the value of the CMD[9:8] at every
transfer command. Doing so the sdo_enabled and sdi_enabled control lines will
store the last active transfer command state and they will be
independent of the current state of the CMD bus. This way we can add
longer time delay to the SDI latching if it's necessary.
The value of the HDL parameter NUM_OF_SDI can be read out from the
register at address 0x0C. The same register contains the value of the
DATA_WIDTH.
The register has the following bit layout:
[15: 0] DATA_WIDTH
[23:16] NUM_OF_SDI
[31:24] 8'b0
Iulia Moldovan
Sergiu Arpadi
laurent-19
Iacob_Liviu
Nick Pillitteri
Istvan Csomortani
Laszlo Nagy
Adrian Costina
stefan.raus
Stanca Pop