Tx path was gated by the FSM also in bypass mode. This must be avoided
since the bypass mode should be independent of the FSM.
Write to bypass fifo only when bypass is enabled
* Added header license for the files that didn't have
* Modified parentheses
* Removed extra spaces at the end of lines
* Fixed parameters list to be each parameter on its line
* Deleted lines after endmodule and consecutive empty lines
* Fixed indentation
Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
Deprecate unused parameters.
Change to MEM_SIZE_LOG2, to support only power of 2 storage sizes for
now. However in the future we might want to add support for non pow2
sizes so register map is not changed.
Change transfer length to -1 value to spare logic.
Change FIFO interface to AXIS to have backpressure, this allows the
implementation of data movement logic in the storage unit and let the
FSM handle high level control an synchronization and control the storage
unit through a control interface.
Refactor FSM to have preparation states where slow storages can be
configured and started ahead of the data handling.
Make bypasss FIFO optional since in some cases causes timing failures
due the missing output register of the memory. This can be targeted in
a later commit.
Hook up underflow/overflow to regmap useful in case of external memory
where rate drops due misconfiguration can be detected.
Cleanup for verilator.
Scripting:
Add HBM and DDR external memory support using util_hbm IP
Replace asym_block_ram with util_do_ram IP
This commit fixes an issue in situations where we provide an oversized
transaction to the data offload in TX mode. Previously, the data offload
would stop accepting new data (wr_ready <= 0) after filling up the
internal storage, and get stuck waiting for the input transaction to
end, thus locking up the device.
This commit addresses that issue by allowing the data offload to consume
the full input transaction, even if the tail of the buffer will be
truncated in the output.
Signed-off-by: David Winter <david.winter@analog.com>
This commit adds a new synthesis option to the design, that controls
whether an internal clock domain crossing will be generated. Disabling
this option allows you to use a synchronization signal that is
synchronized to the write clock domain externally, and possibly shared
between multiple devices.
The default value retains the old behavior.
Signed-off-by: David Winter <david.winter@analog.com>
This commit changes the transfer length register to work in increments of
64 bytes and without offset. The true transfer length can now be
determined by multiplying the value of the transfer_length register with
64.
A value of zero is interpreted as a request for all available storage.
Additionally, this commit fixes an off by one issue that was discovered
during testing of the RX path.
Signed-off-by: David Winter <david.winter@analog.com>
Iulia Moldovan
Iacob_Liviu
Laszlo Nagy
Filip Gherman
Nick Pillitteri
David Winter
Laszlo Nagy
Mihaita Nagy
Adrian Costina
Istvan Csomortani