025420d6f8
library/axi_xcvrlb- xcvr changes
2016-11-23 12:00:13 -05:00
8f562fd069
xcvr updates- board procedure
2016-11-22 14:43:36 -05:00
2ea997c3d5
interfaces- remove channel based pll reset
2016-11-22 11:34:29 -05:00
3dbed492b3
util_adxcvr: expose cpll/qpll as it is
2016-11-22 11:32:37 -05:00
3cbe735bd8
util_adxcvr: regenerate from script
2016-11-22 11:21:04 -05:00
c57ffc9364
axi_adxcvr- separate pll reset from channels
2016-11-22 11:12:54 -05:00
b9795c7033
xilinx/util_adxcvr: Update enablement dependencies
2016-11-22 17:33:40 +02:00
2f2570fcac
axi_i2s: Remove incorrectly inferred interfaces
...
Remove interfaces that were incorrectly inferred by the tools.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-11-18 15:01:29 +01:00
43c74bf55c
axi_i2s: Tie-off optional inputs
...
Tie-off all optional inputs to 0 so that they are driven to a defined value
when not used.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-11-18 15:01:26 +01:00
26907ef1fd
axi_i2s: Remove duplicated clock interface association
...
The I2S interface has a clock associated to it twice, this will generate a
critical warning when using the core, so remove one of them.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-11-18 15:01:24 +01:00
b85a282748
fmcomms11- lane swap
2016-11-16 10:26:47 -05:00
9d6c93a5d8
Fix warnings
2016-11-14 15:17:15 +02:00
12d6e46ae7
clean: Delete deprecated source files
...
The axi_jesd_gt was repleaced by axi_adxcvr IP, which is located
at library/xilinx and library/altera.
The axi_jesd_xcvr was an early version of axi_adxcvr.
The register map is moved to the IP's directory.
2016-11-14 10:43:46 +02:00
c80033cb1b
util_fir_int: removed s_axis_data_tvalid and updated sdrstk
2016-11-11 17:52:19 +02:00
6f4dc92dd2
util_fir_int: Fix channel data assignment
2016-11-11 15:46:17 +02:00
64d1d54ec0
util_fir_int: Update filter, as it's used with ad9361 in CMOS mode
2016-11-10 17:45:03 +02:00
66098b7ae7
util_fir_dec: Update filter, as it's used with ad9361 in CMOS mode
2016-11-10 17:43:04 +02:00
6073cdded4
axi_ad9250: Tie rx_valid to ground
2016-11-10 10:52:37 +02:00
8845aeb6ab
axi_ad9250: Add missing file to Make and script
2016-11-10 10:48:46 +02:00
8493bd4329
axi_ad6676: Update the core, sof interface added
2016-11-10 10:39:33 +02:00
0b58a2a1db
avl_adxcvr- sysclk frequency
2016-11-09 09:21:07 -05:00
48ee720901
avl_adxcvr- a5 requires single transceiver controller
2016-11-08 15:20:01 -05:00
a58597c13a
ad9250 - build fixes
2016-11-08 15:17:54 -05:00
d7357d781b
axi_ad9250 - avalon/axi streaming + sof
2016-11-04 15:30:39 -04:00
ee9c8b884d
avlxcvr- add arria v support
2016-11-04 15:01:19 -04:00
9dc7f16d80
axi_usb_fx3: Added zero length packet capability
2016-11-03 15:29:56 +02:00
1e0fed82f7
alt_serdes- a10 ddio fixes
2016-11-01 12:41:25 -04:00
5eff357568
up_tdd_cntrl: Fix memory map register writes
2016-11-01 10:06:57 +02:00
9f4c5f8060
arradio/ad9361- updates
2016-10-31 15:34:32 -04:00
b94cc8afb1
altera- cmos cores
2016-10-31 13:13:48 -04:00
e0459df0f3
altera -c5 qsys alternative
2016-10-31 11:18:27 -04:00
cc75fa3dfe
altera- java/tcl mess handling
2016-10-31 10:54:07 -04:00
a9d03af771
altera- serdes changes
2016-10-28 14:09:18 -04:00
f2e12cc88f
util_fir_dec: Shifted the output data to the left so that the amplitude remains
...
constant
2016-10-28 15:18:36 +03:00
d9b756e7ad
util_fir_int: Shifted the output data to the left so that the amplitude remains constant
2016-10-28 15:17:30 +03:00
30314e4492
library: Added util_fir_int and util_fir_dec interpolation/decimation filters
2016-10-27 19:31:50 +03:00
8107514dde
altera/common- ad_serdes_clk
2016-10-27 09:41:10 -04:00
f7e3703b98
axi_ad9371- avalon-s interfaces
2016-10-27 09:25:00 -04:00
6f611e0d10
altera/alt_serdes: Add support for Cyclone V
2016-10-25 20:32:51 +03:00
08cef5a745
axi_ad9361: Add Cyclone V SERDES support
2016-10-25 20:24:17 +03:00
5731ba3300
fmcomms11- xcvr updates
2016-10-24 09:51:40 -04:00
de0c487195
axi_ad9684: Add Altera support for the core
2016-10-24 11:43:22 +03:00
3f3606d318
axi_ad9122: Add Altera support for the core
2016-10-24 11:43:12 +03:00
aa46de5e5e
adi_ip_alt: Add ad_generate_module_inst proc
...
Add a tcl process, which can be used to generate custom module
names during the generation phase. This will be used to create
different ad_serdes_clk module, in case when independent IOPLLs are
needed for TX and RX.
2016-10-24 11:43:00 +03:00
707038937a
alt_serdes: Add additional parameters
...
Add additional parameters to keep the top of ad_serdes_* modules
consistant through differente carriers.
2016-10-24 11:42:43 +03:00
8dbfe9258f
axi_ad9162: Delete duplicated port
2016-10-21 13:47:01 +03:00
0beecea02d
util_adxcvr- ultrascale updates
2016-10-19 13:06:10 -04:00
72c05e8635
axi_dmac: Fix constraints for ultrascale
...
Replace "PRIMITIVE_SUBGROUP == flop" with "IS_SEQUENTIAL" as the former is
series7 specific while the later works on all platforms. This fixes the
axi_dmac timing constraints for ultrascale based platforms.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-10-19 14:00:54 +02:00
ecc0addb8c
scripts/adi_ip_alt.tcl: Script is case insensitive for its arguments
2016-10-18 11:25:06 +03:00
bf949f1a88
axi_xcvrlb- xcvr updates
2016-10-17 16:16:57 -04:00
Rejeesh Kutty
Istvan Csomortani
Lars-Peter Clausen
AndreiGrozav
Adrian Costina