158c10df34
projects: starndadize the jesd make parameters
2022-09-13 11:53:21 +03:00
482f0489a3
scripts: Merge adi_env.tcl into a single file
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Move the new adi_env.tcl file from hdl/projects/scripts into hdl/scrips
2022-08-08 13:52:54 +03:00
171daab8f2
ad9081_fmca_ebz: a10soc: Update resistor change comment
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A board rework is required so the clocks, chip selects or sync signal reach the part correctly. Without this the link will not come up.
2022-06-21 14:19:58 +03:00
bdd5686e95
ad9081_fmca_ebz/a10soc: Make second sync CMOS and GPIO controllable
2022-05-26 09:13:05 +03:00
8df1d8eade
ad9081_fmca_ebz: Update parameter description
2022-03-11 13:16:22 +02:00
adad6c930d
ad9081_fmca_ebz_qsys.tcl: Add RX_LANE_RATE and TX_LANE_RATE parameters
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For ad9081/a10soc project, the RX_LANE_RATE and TX_LANE_RATE were computed
from SAMPLE_RATE. Remove SAMPLE_RATE and add RX_LANE_RATE and TX_LANE_RATE
as parameters. Update also computation examples from comments.
Signed-off-by: stefan.raus <stefan.raus@analog.com>
2021-11-12 13:04:57 +02:00
af3e1c7003
ad9081_fmca_ebz/a10soc: Np 12 support
2021-02-05 15:24:15 +02:00
0fd5590e56
ad9081_fmca_ebz: a10soc: Initial version
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Parametrizable project with default profile of:
M=8 L=4 SampleRate=250 MSPS
LaneRate=10 Gbps
2021-02-05 10:24:59 +02:00
LIacob106
Laszlo Nagy
Laszlo Nagy
stefan.raus