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7 Commits (4e8c816d3f1e1e3a821dd83b20650d796034be61)

Author SHA1 Message Date
Laszlo Nagy 7b2ba41bdd ad9081_fmca_ebz/vcu118: Adjust QPLL params and diff swing 
This commit fixes the 16.5Gbps lane rate case where the link drops
after few seconds an initial successful link up happens.
A few seconds delayed calibration process can workaround this but with
having the differential drivers swing increased this is no longer
required.
 2021-05-14 15:39:40 +03:00
Laszlo Nagy 0d9e38bdbe ad9081_fmca_ebz: Update path to common block design 
Use absolute paths so ad9082 wrapper project can include the
system_bd.tcl instead of duplicating code.
 2021-05-14 15:39:40 +03:00
Laszlo Nagy bd6ec360e2 ad9081_fmca_ebz/vcu118: Set XCVR params for 204C link 
Set XCVR parameter for 204C 24.75 Gbps with a  dynamic range of 10Gbps..24.75Gpbs

Organize XCVR params based on lane rate
 2021-05-14 15:39:40 +03:00
Laszlo Nagy d0f8a81b2f ad9081_fmca_ebz: Np 12 support 
204B functional
204C functional
 2021-02-05 15:24:15 +02:00
sergiu arpadi acbbd4636a sysid: Upgrade framework, header/ip are now at 2/1.1.a 
Unify tcl scripts; rename adi_pd_intel.tcl to adi_pd.tcl
add git branch to internal use area; update log prints;
update xilixn projects; fix cn0506 sysid script;
 2021-01-20 01:02:56 +02:00
Sergiu Arpadi d8ab27b2af sysid: Remove cstring init string 2020-09-30 19:12:24 +03:00
Laszlo Nagy b1f62f09ac ad9081_fmca_ebz:vcu118: initial version 
Use over-writable parameters from the environment.

      e.g.
        make JESD_MODE=64B66B RX_RATE=24.75 TX_RATE=12.375 REF_CLK_RATE=375 RX_JESD_L=4 TX_JESD_L=4
        make JESD_MODE=64B66B RX_RATE=16.22016 TX_RATE=16.22016 REF_CLK_RATE=245.76 RX_JESD_M=8 RX_JESD_L=2 TX_JESD_M=16 TX_JESD_L=4
        make JESD_MODE=8B10B  RX_JESD_L=4 RX_JESD_M=8 TX_JESD_L=4 TX_JESD_M=8
 2020-03-10 18:19:03 +02:00