LIacob106
3e297f54dd
projects/adrv9009zu11eg: expose jesd params to make and add FMCOMMS8 parameter
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Expose JESD parameters to make.
Add FMCOMMS8 parameter.
Changed the name of the observation path to match the rest of the repo.
Replace old dac_data_width formula with a more generic one.
2022-09-26 14:26:31 +03:00
Iacob_Liviu
482f0489a3
scripts: Merge adi_env.tcl into a single file
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Move the new adi_env.tcl file from hdl/projects/scripts into hdl/scrips
2022-08-08 13:52:54 +03:00
Iulia Moldovan
961ebe0cc2
projects: Update .v files according to guideline
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Deleted lines after endmodule and consecutive empty lines.
Modified parentheses, extra spaces.
Fixed indentation.
Fixed parameters list to be each parameter on its line.
Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-06-28 18:06:56 +03:00
Adrian Costina
d40db9e204
adrv9009zu11eg: Added additional GPIOs and CS to the GPIO expander
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This should integrate seamlessly with SYNCHRONA14
2022-04-01 10:24:04 +03:00
Laszlo Nagy
fe58a5fb47
adrv9009zu11eg/adrv2crr_fmcomms8: Add clock buffers for core clocks
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The IBUFGDS primitive is deprecated in UltraScale devices.
Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
2021-11-11 17:33:10 +02:00
Adrian Costina
591a23156b
Makefiles: Update header with the appropriate license
2021-09-16 16:50:53 +03:00
Sergiu Arpadi
40baa63f0f
adrv2crr_fmcomms8: Fix system_top.v
2021-03-19 17:56:28 +02:00
Sergiu Arpadi
6f2f2b8626
makefile: Regenerate make files
2021-01-20 01:02:56 +02:00
sergiu arpadi
acbbd4636a
sysid: Upgrade framework, header/ip are now at 2/1.1.a
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Unify tcl scripts; rename adi_pd_intel.tcl to adi_pd.tcl
add git branch to internal use area; update log prints;
update xilixn projects; fix cn0506 sysid script;
2021-01-20 01:02:56 +02:00
Istvan Csomortani
e41ba7f6f5
adrv9009zu11eg: Use adi_project_create instead of adi_project
2021-01-15 15:26:43 +02:00
Adrian Costina
ecd880d44c
adrv9009zu11eg:fmcomms8: Fix SPI timing constraint
2020-11-05 17:42:41 +02:00
Adrian Costina
9093a8c428
library: Move ad_iobuf to the common library, as it's not Xilinx specific
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Updated all system_project and Makefiles
2020-11-02 16:13:35 +02:00
Sergiu Arpadi
d8ab27b2af
sysid: Remove cstring init string
2020-09-30 19:12:24 +03:00
Adrian Costina
c4b94fc564
adrv9009zu11eg: Add S JESD204 parameter for the projects
2020-02-18 11:19:02 +02:00
Adrian Costina
645696e5b4
adrv9009zu11eg: Extend SPI connection to the PL HD PINS expansion
2020-02-18 11:19:02 +02:00
Adrian Costina
d2817863a1
adrv9009zu11eg: Add FMCOMMS8 support
2020-02-18 11:19:02 +02:00