Rejeesh Kutty
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5176e427a1
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common/a10soc- add project create tcl procedure
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2017-06-06 12:24:13 -04:00 |
|
Rejeesh Kutty
|
d10faabc3f
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a10soc- 16.1- hsp sdram reset
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2017-05-17 16:30:37 -04:00 |
|
Rejeesh Kutty
|
ebeebdddf0
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altera- infer latest versions
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2017-05-12 13:40:14 -04:00 |
|
Rejeesh Kutty
|
deb8635854
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adrv9371x/altera- gpio equivalency fix
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2017-03-27 16:37:55 -04:00 |
|
Rejeesh Kutty
|
50552ce7d6
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adrv9371x- altera updates
|
2016-10-27 09:25:00 -04:00 |
|
Rejeesh Kutty
|
f752f0c9d7
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a10soc- xcvr updates
|
2016-10-27 09:25:00 -04:00 |
Adrian Costina
|
e40311eee9
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adrv9371x: A10soc, connected DMAs through 128 bit SDRAM0 port at 175MHz
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2016-09-29 09:14:37 +01:00 |
|
Adrian Costina
|
2d307d5f58
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a10soc: Added system reset bridge. Using F2SDRAM port used in the previous Qsys design
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2016-09-24 10:06:35 +03:00 |
|
Adrian Costina
|
40c9fc92c1
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a10soc: Switched to tcl flow
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2016-09-08 11:31:06 +03:00 |