0374a7c1ac
ad9081_fmca_ebz/vcu118: Added common 204C use cases as example
2021-02-05 15:24:15 +02:00
ddd8a14790
ad9081_fmca_ebz: Remove system reset from Xilinx PHY
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Reset in device clock domain caused timing failures.
Since link reconfiguration is not supported the reset is not required.
2021-02-05 15:24:15 +02:00
af3e1c7003
ad9081_fmca_ebz/a10soc: Np 12 support
2021-02-05 15:24:15 +02:00
bb9eafceef
ad9081_fmca_ebz/zcu102: Add case analysis to select correct out clock frequency
2021-02-05 15:24:15 +02:00
d0f8a81b2f
ad9081_fmca_ebz: Np 12 support
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204B functional
204C functional
2021-02-05 15:24:15 +02:00
0fd5590e56
ad9081_fmca_ebz: a10soc: Initial version
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Parametrizable project with default profile of:
M=8 L=4 SampleRate=250 MSPS
LaneRate=10 Gbps
2021-02-05 10:24:59 +02:00
6f2f2b8626
makefile: Regenerate make files
2021-01-20 01:02:56 +02:00
acbbd4636a
sysid: Upgrade framework, header/ip are now at 2/1.1.a
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Unify tcl scripts; rename adi_pd_intel.tcl to adi_pd.tcl
add git branch to internal use area; update log prints;
update xilixn projects; fix cn0506 sysid script;
2021-01-20 01:02:56 +02:00
da9828a63e
ad9081:zcu102: Expose parameters to environment
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Allow setting project parameters from the environment.
2021-01-19 17:10:08 +02:00
3dd370a27c
ad9081_fmca_ebz: enable xbar in DAC TPL
2020-11-27 09:45:11 +02:00
ad755788a0
ad9081_fmca_ebz/zc706: Initial version
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M=8 L=4 SampleRate=250 MSPS
LaneRate=10 Gbps
2020-11-12 15:46:27 +02:00
e9f319e3d7
ad9081_fmca_ebz: HP0 is already initialized in ZC706
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On carriers like ZC706 the HP0 interconnect is in already in use so it must
not be initialized here.
2020-11-12 15:46:27 +02:00
9093a8c428
library: Move ad_iobuf to the common library, as it's not Xilinx specific
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Updated all system_project and Makefiles
2020-11-02 16:13:35 +02:00
4026eaa19b
ad9081_fmca_ebz: Fix device clocks termination
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The device clocks are AC coupled LVDS lines without external termination.
For proper operation internal differential termination must be enabled,
the DQS_BIAS will DC bias the AC coupled signal to VCCO/2 (1.8/2) 0.9V
2020-10-06 16:13:21 +03:00
d8ab27b2af
sysid: Remove cstring init string
2020-09-30 19:12:24 +03:00
e8f6523197
ad9081_fmca_ebz: adapt to renamed tpl core
2020-05-20 19:08:25 +03:00
cbb23c7b67
ad9081_fmca_ebz: fix Xilinx PHY resets
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Avoid clock domain crossing on resets.
2020-04-23 17:21:05 +03:00
e112a03d85
ad9081_fmca_ebz: Whitespace cleanup
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Clear extra lines and whitespaces at end of lines.
2020-04-23 17:21:05 +03:00
7df4caf8b0
ad9081_fmca_ebz: Added parameter description
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Add parameter description to project and common block design file
2020-04-23 17:21:05 +03:00
e433d3f808
ad9081_fmca_ebz: expose PLL selection as a parameter
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On the Xilinx PHY the available PLL options depends on the lane rate.
Encoding is:
0 - CPLL
1 - QPLL0
2 - QPLL1
Since the selection of line rate is available from the project also the
PLL selection must be exposed.
2020-04-23 17:21:05 +03:00
b774e1ca7d
ad9081_fmca_ebz: enable IQ rotation
2020-04-03 11:16:37 +03:00
b1f62f09ac
ad9081_fmca_ebz:vcu118: initial version
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Use over-writable parameters from the environment.
e.g.
make JESD_MODE=64B66B RX_RATE=24.75 TX_RATE=12.375 REF_CLK_RATE=375 RX_JESD_L=4 TX_JESD_L=4
make JESD_MODE=64B66B RX_RATE=16.22016 TX_RATE=16.22016 REF_CLK_RATE=245.76 RX_JESD_M=8 RX_JESD_L=2 TX_JESD_M=16 TX_JESD_L=4
make JESD_MODE=8B10B RX_JESD_L=4 RX_JESD_M=8 TX_JESD_L=4 TX_JESD_M=8
2020-03-10 18:19:03 +02:00
f3a7fd8b0d
ad9081_fmca_ebz:zcu102: initial version
2020-03-10 18:19:03 +02:00
f3630dd95b
ad9081_fmca_ebz: common block design
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Parametrizable block design with selectable JESD physical layer between
Xilinx Phy and ad_utilxcvr.
2020-03-10 18:19:03 +02:00
Laszlo Nagy
Sergiu Arpadi
Adrian Costina