Rejeesh Kutty
|
50d018fc11
|
arradio- rfifo/wfifo added
|
2016-05-18 13:24:13 -04:00 |
|
Rejeesh Kutty
|
e345953bdd
|
arradio- updates
|
2016-05-16 12:19:38 -04:00 |
Adrian Costina
|
72151bb1a6
|
a10gx: Updated base design to include MMU
|
2016-05-13 18:44:41 +03:00 |
|
Rejeesh Kutty
|
f3f5353944
|
zcu102- updates
|
2016-05-10 15:40:41 -04:00 |
|
Rejeesh Kutty
|
16e3a0e569
|
zcu102- updates
|
2016-05-10 15:40:41 -04:00 |
|
Rejeesh Kutty
|
e1350018da
|
zcu102- updates
|
2016-05-10 15:40:41 -04:00 |
|
Rejeesh Kutty
|
a6411dbd63
|
zcu102- added
|
2016-05-10 15:40:41 -04:00 |
|
Rejeesh Kutty
|
e8fbdd0f5d
|
zcu102: zynq ultrascale
|
2016-05-10 15:40:41 -04:00 |
|
Rejeesh Kutty
|
0041bf69be
|
c5soc- remove unused hps ports
|
2016-05-09 13:54:08 -04:00 |
|
Rejeesh Kutty
|
89b20f2a35
|
c5soc- remove unused hps ports
|
2016-05-09 13:54:08 -04:00 |
AndreiGrozav
|
8d72b645ae
|
fmcomms2/common: Remove ila_tdd block
|
2016-05-09 10:28:10 +03:00 |
Istvan Csomortani
|
b0538a03a2
|
Make: Update
|
2016-05-06 16:44:24 +03:00 |
|
Istvan Csomortani
|
4863a04132
|
axi_adc/dacfifo: Split the intergration script file
Split the integration script file into two separate script files. Rename the
integration processes names to be more meaningful.
|
2016-05-05 09:53:55 +03:00 |
|
Rejeesh Kutty
|
ddfaff2cf5
|
fmcomms2/a10soc: compile version
|
2016-05-04 13:42:12 -04:00 |
|
Rejeesh Kutty
|
f4e5965936
|
fmcomms2/a10soc: ip updates
|
2016-05-04 13:42:12 -04:00 |
|
Rejeesh Kutty
|
92dcce1674
|
a10soc: default ports
|
2016-05-04 13:42:12 -04:00 |
|
AndreiGrozav
|
be74db656c
|
ad6674evb, fmcadc2, fmcadc4, fmcadc5, fmcjesdadc1:
Update system_project.tcl scripts to correctly select the necessary
constraint files
|
2016-05-04 19:37:33 +03:00 |
|
AndreiGrozav
|
3ca3414522
|
fmcadc2: Fixed bus data width
|
2016-05-04 19:20:01 +03:00 |
|
AndreiGrozav
|
9104b2cc60
|
ad6676evb, fmcadc2, fmcadc4, fmcadc5,...
ad6676evb, fmcadc2, fmcadc4, fmcadc5, fmcjesdadc1: Remove unused
set_proprieties
|
2016-05-04 19:13:25 +03:00 |
|
Rejeesh Kutty
|
385ed31a45
|
make files update
|
2016-04-29 10:17:35 -04:00 |
|
Rejeesh Kutty
|
61b531b1c1
|
a10soc device update
|
2016-04-29 10:17:35 -04:00 |
|
Rejeesh Kutty
|
664ea16a0f
|
ccpci- carrier changes
|
2016-04-27 16:26:11 -04:00 |
|
Rejeesh Kutty
|
e790e4c3ae
|
a10soc- complete qsys
|
2016-04-25 12:56:19 -04:00 |
|
Rejeesh Kutty
|
bfa6fe2a40
|
a10soc- updates
|
2016-04-25 11:23:16 -04:00 |
|
Rejeesh Kutty
|
28159aeec9
|
a10soc- updates
|
2016-04-25 11:11:46 -04:00 |
|
Rejeesh Kutty
|
0a3967b886
|
a10soc- updates
|
2016-04-25 10:53:26 -04:00 |
|
Rejeesh Kutty
|
d36d1263c5
|
a10soc- updates
|
2016-04-25 10:50:09 -04:00 |
|
Rejeesh Kutty
|
2a5f31d26b
|
fmcomms2/a10soc- copy
|
2016-04-22 15:15:44 -04:00 |
|
Rejeesh Kutty
|
82c4f75f13
|
a10soc- a10gx copy
|
2016-04-22 10:39:21 -04:00 |
|
Rejeesh Kutty
|
7a4a7edfba
|
daq2/a10gx: 10AX115S3F45E2SGE3 version
|
2016-04-20 16:07:41 -04:00 |
|
Rejeesh Kutty
|
e00236e5fd
|
daq2/a10gx: 10AX115S3F45E2SGE3 version
|
2016-04-20 16:04:46 -04:00 |
|
Rejeesh Kutty
|
8b2542b181
|
daq2/a10gx: 10AX115S3F45E2SGE3 version
|
2016-04-20 16:01:12 -04:00 |
|
AndreiGrozav
|
679d471d75
|
Merge branch 'hdl_2016_r1' into dev
hdl_2016_r1 contains IP core upgrades to Vivado 2015.4.2 and hdmi_tx improvements.
|
2016-04-19 18:05:50 +03:00 |
|
Adrian Costina
|
402253d308
|
usb_fx3: Updated design to include the GPIF II interface
|
2016-04-19 15:52:30 +03:00 |
|
Istvan Csomortani
|
8a574cd8ba
|
zc706_system_plddr3.tcl : Add integration process for the AXI_DAC_FIFO
|
2016-04-19 11:30:52 +03:00 |
|
AndreiGrozav
|
c291f8f107
|
daq1: Updated design to 2015.4
|
2016-04-14 23:36:47 +03:00 |
|
AndreiGrozav
|
469b4ea5e8
|
fmcadc5: Updated design to 2015.4
|
2016-04-14 23:18:23 +03:00 |
|
AndreiGrozav
|
62bd057106
|
fmcadc5/common: Update common design to 2015.4
|
2016-04-14 23:01:38 +03:00 |
|
Rejeesh Kutty
|
a88ced8136
|
pzsdr1: lvds/cmos updates
|
2016-04-11 16:18:29 -04:00 |
|
Rejeesh Kutty
|
3006c5a223
|
make updates
|
2016-04-11 16:14:59 -04:00 |
|
Rejeesh Kutty
|
736bbdd95a
|
pzsdr1- io updates
|
2016-04-11 16:12:21 -04:00 |
|
Rejeesh Kutty
|
8a5a5082f3
|
pzsdr1- io updates
|
2016-04-11 16:12:09 -04:00 |
|
Rejeesh Kutty
|
8e689f4594
|
pzsdr1- lvds/cmos constraints
|
2016-04-11 16:00:18 -04:00 |
|
Rejeesh Kutty
|
7e807d83b1
|
pzsdr1- cmos mode
|
2016-04-11 15:58:29 -04:00 |
|
Rejeesh Kutty
|
bf6ef4e5f3
|
board- add disconnect
|
2016-04-11 15:33:00 -04:00 |
|
Rejeesh Kutty
|
68bc647472
|
pzsdr1- ddr board delays update
|
2016-04-06 15:30:27 -04:00 |
|
AndreiGrozav
|
21208ca208
|
Makefiles: Update Makefiles
|
2016-03-31 12:37:47 +03:00 |
|
Istvan Csomortani
|
1fab6ce477
|
daq2/common: Add util_dacfifo/dac_xfer_out control
|
2016-03-29 16:55:33 +03:00 |
|
Istvan Csomortani
|
255b0ebd40
|
util_dacfifo: Add dac_xfer_out control
The dac_xfer_out control signal is asserted while the DAC reads back data. Should be connected to upack/dma_xfer_in.
|
2016-03-29 16:50:00 +03:00 |
|
Adrian Costina
|
657144d9a7
|
a10gx: Updated base design and DAQ2 to the new revision of the a10gx board
- tried using ATX PLL and fPLL for TX transceiver clocks, but could not get them to lock
- CMU PLL works correctly as temporary solution
|
2016-03-28 13:21:36 +03:00 |