425e803364
license: Fix a spelling mistake
2018-04-11 15:09:54 +03:00
2926a6aaf9
altera/ad_mem_asym: Delete it, QSYS flow is used
2017-09-25 08:57:26 +01:00
8dc2161870
alt_mem_asym: Set read latency to 1 clock cycle
...
In its default configuration the ram_2port module as a read latency of 2
clock cycles. Both the read address as well as the output data are
registered.
This is not the behavior that is expected from the alt_mem_asym module and
causes incorrect behavior and data corruption in the util_adc_fifo.
Disable the data output register to get a read latency of 1 clock cycle.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-13 10:28:11 +02:00
d7e87a60a9
Remove executable flag from non-executable files
...
All of these files are source code and are not executable standalone.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-28 17:56:07 +02:00
36a9ea40b1
altera- remove lvds/serdes/cmos cores
2017-07-20 14:19:40 -04:00
e1c95b23ea
alt_serdes- remove c5 support
2017-07-20 14:16:32 -04:00
a27b30d380
library- remove c5 cores
2017-07-20 14:12:00 -04:00
6c986d9b6a
hdl/library- fix syntax errors/synthesis warnings
2017-07-20 14:07:32 -04:00
227bd3edfe
alt_ifconv-- qsys workaround
2017-06-09 16:17:34 -04:00
41d305b6b6
up_clock_mon- name changes
2017-06-06 11:36:18 -04:00
84b2ad51e2
license: Add some clarification to the header license
2017-05-31 18:18:56 +03:00
85ebd3ca01
license: Update license terms in hdl source files
...
Fix a few gramatical error, fix the path of the top level license
files.
2017-05-29 09:55:41 +03:00
aaae350b3d
alt_serdes- 16.1 updates
2017-05-26 11:00:07 -04:00
25e42c49d6
library: move alt cores to common
2017-05-26 10:51:25 -04:00
10898d6618
constraints: Split the regmap CDC constraint into separate file
2017-05-25 15:12:16 +03:00
6dbbe2f1ca
altera/ad_mem_asym: Fix grounded bus for marco instance
...
The "'b0" constant will be translate as a 32 bit width vector by
ModelSim, and will throw a buswidth mismatch error. Tie the data_b
bus to zero, using its width parameter.
2017-05-25 15:12:09 +03:00
80a3f45b9f
alt_mul- qsys replacement
2017-05-18 10:38:48 -04:00
6649b23bc8
alt-mem-asym - replace mega function cores
2017-05-17 16:13:26 -04:00
bea72232a3
alt_mem_asym- qsys component
2017-05-17 16:13:26 -04:00
9055774795
all: Update license for all hdl source files
...
All the hdl (verilog and vhdl) source files were updated. If a file did not
have any license, it was added into it. Files, which were generated by
a tool (like Matlab) or were took over from other source (like opencores.org),
were unchanged.
New license looks as follows:
Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
Each core or library found in this collection may have its own licensing terms.
The user should keep this in in mind while exploring these cores.
Redistribution and use in source and binary forms,
with or without modification of this file, are permitted under the terms of either
(at the option of the user):
1. The GNU General Public License version 2 as published by the
Free Software Foundation, which can be found in the top level directory, or at:
https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
OR
2. An ADI specific BSD license as noted in the top level directory, or on-line at:
https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
2017-05-17 11:52:08 +03:00
468965a792
altera/ad_cmos_in: Define supported DEVICE_TYPE options
2017-04-25 12:07:33 +03:00
52305f74c8
altera/ad_cmos_in|out: Delete redundant parameter
2017-04-25 12:06:33 +03:00
1c23cf4621
all: Update verilog files to verilog-2001
2017-04-13 11:59:55 +03:00
3586397f57
altera/common- add asymmetric fifo
2017-03-01 15:35:04 -05:00
0715c962f1
altera/ad_serdes: Fix net alignment for rx_out at ad_serdes_in
2016-12-06 15:24:19 +02:00
1e0fed82f7
alt_serdes- a10 ddio fixes
2016-11-01 12:41:25 -04:00
b94cc8afb1
altera- cmos cores
2016-10-31 13:13:48 -04:00
e0459df0f3
altera -c5 qsys alternative
2016-10-31 11:18:27 -04:00
cc75fa3dfe
altera- java/tcl mess handling
2016-10-31 10:54:07 -04:00
a9d03af771
altera- serdes changes
2016-10-28 14:09:18 -04:00
8107514dde
altera/common- ad_serdes_clk
2016-10-27 09:41:10 -04:00
6f611e0d10
altera/alt_serdes: Add support for Cyclone V
2016-10-25 20:32:51 +03:00
2d93d787ab
altera/ad_cdfilter: Update interface to Verilog 2001 standard
2016-10-11 17:59:21 +03:00
d41945f568
altera/ad_serdes: Add support for any SERDES factor less than 8
2016-10-11 17:59:14 +03:00
6510f92c12
ad_serdes : Cosmetic changes
2016-09-16 14:45:39 +03:00
13a35f7a2a
altera/ad_serdes_clk: The IO_PLL reset is active heigh
2016-09-16 14:20:39 +03:00
858ea09048
altera/ad_serdes_in: Fix some typos
2016-09-16 10:56:16 +03:00
a2d15acb89
ad_serdes- altera/xilinx sync
2016-09-15 13:33:55 -04:00
63696c1a28
alt_serdes- data-width parameter
2016-09-15 11:12:18 -04:00
02dfd2d2e2
altera/ad_serdes_out- sample transmit order
2016-09-15 10:28:34 -04:00
5986f45cba
altera/ad_serdes_out- updates
2016-09-15 09:38:11 -04:00
16046a984c
alt_serdes- updates
2016-09-14 12:05:48 -04:00
4a6b554c0a
ad_serdes- updates
2016-09-14 11:12:53 -04:00
a0318ae868
ad_serdes_clk- syntax errors
2016-09-13 14:02:11 -04:00
2a34f9baa8
alt-serdes, in & out
2016-09-12 11:45:23 -04:00
9e0c39a71b
alt_serdes_clk- changes
2016-09-12 10:30:28 -04:00
f4be0524b4
altera/common: Add SERDES related modules
2016-09-09 18:04:41 +03:00
6a8ca8107a
common: Added common ad_dcfilter stub for altera.
2016-08-16 17:37:16 +03:00
90ac7b7ac9
lib_refactoring: Move all Altera module to library/altera/common
...
Move all Altera modules to library/altera/common, delete the
deprecated wrapper files
2016-08-08 15:07:01 +03:00
cb9af99c5d
lib_refactoring: Add ad_mul.v for Altera
2016-08-08 15:06:48 +03:00
Istvan Csomortani
Lars-Peter Clausen
Rejeesh Kutty
AndreiGrozav
Adrian Costina