Rejeesh Kutty
|
5f21f54463
|
fmcjesdadc1: zc706 version
|
2014-08-25 14:28:57 -04:00 |
|
Rejeesh Kutty
|
cb29b83b05
|
a5gt: updates to match a5gt
|
2014-08-25 10:46:59 -04:00 |
|
Rejeesh Kutty
|
76ffb939e5
|
zc706: ad9625 copy
|
2014-08-22 11:24:24 -04:00 |
|
Rejeesh Kutty
|
39bb7ca231
|
a5soc: fmcjesdadc1+hdmi version
|
2014-08-14 09:05:38 -04:00 |
|
Rejeesh Kutty
|
96969079ce
|
a5soc: fixes for 14.0 and spi conflicts
|
2014-08-11 16:46:37 -04:00 |
|
Rejeesh Kutty
|
60dd14bcdb
|
a5soc: removed jtag master control
|
2014-07-01 12:27:37 -04:00 |
|
Rejeesh Kutty
|
92e525d573
|
ad9250: register map updates
|
2014-06-25 15:24:48 -04:00 |
|
Rejeesh Kutty
|
4d4f66fbdd
|
a5soc: increase pipeline for qsys
|
2014-05-04 10:38:53 -04:00 |
|
Rejeesh Kutty
|
b55d0d7ad1
|
a5soc: constraints for false paths
|
2014-04-30 16:14:30 -04:00 |
|
Rejeesh Kutty
|
0b1ce14842
|
a5soc: basic hardware build
|
2014-04-30 12:40:27 -04:00 |
|
Rejeesh Kutty
|
99d66e7580
|
a5soc: initial-copy version
|
2014-04-30 12:40:26 -04:00 |
|
Rejeesh Kutty
|
33979fc533
|
fixes to improve timing - fifo for clock domain transfers
|
2014-04-04 13:49:53 -04:00 |
|
Rejeesh Kutty
|
6a19b34a00
|
a5gt: added tightly coupled memory
|
2014-04-03 20:50:17 -04:00 |
|
Rejeesh Kutty
|
12e5cc91bd
|
make signaltap/timing part of the flow
|
2014-04-03 20:50:15 -04:00 |
|
Rejeesh Kutty
|
e85153b5dd
|
altera hal version
|
2014-04-01 21:12:11 -04:00 |
|
Rejeesh Kutty
|
04df908fbf
|
altera-fmcjesdadc1 initial checkin
|
2014-04-01 12:01:57 -04:00 |
|
Rejeesh Kutty
|
0d678b89ed
|
altera a5gt fmcjesdadc1 setup
|
2014-04-01 11:46:37 -04:00 |