f1a0946a5d
daq3: Delete redundant timing constraint
...
Delete none generic timing constarints related to the memory interface.
Set optimization mode to default.
2020-08-11 10:14:18 +03:00
6e6f1347d7
project/scripts: Rename adi_project_alt.tcl to adi_project_intel.tcl
2019-06-29 06:53:51 +03:00
ec67a381e4
adi_project: Rename the process adi_project_altera to adi_project
2019-06-29 06:53:51 +03:00
deb366d169
daq2|3: Set up OPTIMIZATION_MODE to improve timing
...
There are random timing violations on the A10GX board using the
DAQ3 and DAQ2 projects.
Setting the synthesis/implementation strategy to "HIGH PERFORMANCE
EFFORT" increases the success rate of the timing closure significantly.
2018-06-06 08:33:20 +01:00
22df03f9a4
daq3: A10GX, overconstrained failing paths
2017-10-28 08:21:50 +01:00
6100a697e8
daq3/a10gx- alt 16.1 updates
2017-06-07 10:23:20 -04:00
0e002f2f31
daq3_a10gx: Set XCVR Tx/RX clk/data voltage levels at 1V
2017-03-09 08:50:55 +02:00
fcd56a2f90
daq3/a10gx: Update project to the new GT framework
...
- Update common script
- Update system_top, some port names were changed
- Update constraint files
2016-10-10 16:22:08 +03:00
92c580a84d
daq3: A10GX, updated project to the TCL flow
2016-07-08 12:00:37 +03:00
07316a905e
daq3/a10gx: sysref is lvds
2015-12-14 09:29:10 -05:00
dc84a9ad82
daq3/a10gx: updates
2015-12-10 16:06:14 -05:00
b0fef1122e
daq3/a10gx: copy
2015-12-10 09:41:37 -05:00
Istvan Csomortani
Adrian Costina
Rejeesh Kutty
AndreiGrozav