* Updated action to run only in PRs on master branch, on library/ and
projects/ paths
* Edited the text for the printed warnings
* Updated the version for the checkout action from v2 to v3
Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
Added the files generated by Quartus Pro 21.2, 20.1 and Platform Designer for each of the versions. The files added are generated and removed by make.
Signed-off-by: Liviu.Iacob <liviu.iacob@analog.com>
- Added an utility buffer in order to generate the 50Mhz DRP clock.
- 'addn_ui_clockout4' will be used to generate the higher frequency 'sys_mb' clock for Microblaze.
Signed-off-by: Filip Gherman <Filip.Gherman@analog.com>
Increased the Microblaze performance for the VCU118 carrier:
- Increased the size of Instruction Cache and Data Cache to 64kB
Increased the Microblaze clock frequency:
- Using the DDR4 Controller to generate a new sys_mb_clk of 214 MHz to drive all the Microblaze interfaces at higher frequencies
Signed-off-by: Filip Gherman <Filip.Gherman@analog.com>
Almost all the IPs found in library generate a bd folder when they are built. Updated the .gitignore so that it does not appear as an untracked file.
Also, changes to tracked bd.tcl files (ex:axi_dmac) will still appear as modified files.
Signed-off-by: Liviu.Iacob <liviu.iacob@analog.com>
Created a virtual clock to constrain cnv_en.
Given that the cnv_en should be asserted only once per 8 clock
cycles and only the rise edge is of interest, we can constrain
the path as multicycle path.
Because the inferface signals which pass through the eval board's
Arduino connector are connected to level shifters the design
will not work at the maximum clk frequency of 48MHz. The maximum
tested frequency is 24MHz.
On architectures with ports that support cache coherency, the AWCACHE
signal must be set to indicate that transactions are cached. This patch
adds a parameter allowing AWCACHE to be set on an AXI4 destination port.
Address size and memory ranges are automatically computed by the
external storage interfacing IP (util_hbm) based on the storage size and
base address so this parameter is redundant.
The internal bypass FIFO has poor timing performance,
when using HBM data can be passed always through the external memory
without storage length constraints, so no need for the internal bypass FIFO.
Make the storage type over writable so it can be set specifically
to carriers.
Address width of external memory AXI master is calculated in the
interfacing core (util_hbm) so that parameters is removed.
The HBM interfacing core requires a 450MHz clock, make it part of the
base design.
The clock can't be obtained from the DDR controller so a clock wizard is
used instead.
Deprecate unused parameters.
Change to MEM_SIZE_LOG2, to support only power of 2 storage sizes for
now. However in the future we might want to add support for non pow2
sizes so register map is not changed.
Change transfer length to -1 value to spare logic.
Change FIFO interface to AXIS to have backpressure, this allows the
implementation of data movement logic in the storage unit and let the
FSM handle high level control an synchronization and control the storage
unit through a control interface.
Refactor FSM to have preparation states where slow storages can be
configured and started ahead of the data handling.
Make bypasss FIFO optional since in some cases causes timing failures
due the missing output register of the memory. This can be targeted in
a later commit.
Hook up underflow/overflow to regmap useful in case of external memory
where rate drops due misconfiguration can be detected.
Cleanup for verilator.
Scripting:
Add HBM and DDR external memory support using util_hbm IP
Replace asym_block_ram with util_do_ram IP
This IP replaces the ad_mem_asym module as storage element for the data
offload.
Having standard AXIS interface for data will allow
implementation of storages on UltraRAM.
This IP serves as storage interfacing element for external memories like
HBM or DDR4 which have AXI3 or AXI4 data interfaces.
The core leverages the axi_dmac as building blocks by merging an array of
simplex DMA channels into duplex AXI channels. The core will split the
incoming data from the source AXIS interface to multiple AXI channels,
and in the read phase will merge the multiple AXI channels into a single
AXIS destination interface.
The number of duplex channels is set by syntheses parameter and must be
set with the ratio of AXIS and AXI3/4 interface.
Underflow or Overflow conditions are reported back to the data offload
through the control/status interface.
In case multiple AXI channels are used the source and destination AXIS
interfaces widths must match.
Iulia Moldovan
Laszlo Nagy
Liviu.Iacob
ladace
PopPaul2021
Ionut Podgoreanu
Filip Gherman
Laszlo Nagy
Adrian Costina
Benjamin Menkuec
AndreiGrozav
Stanca Pop
sergiu arpadi
Mathias Tausen
Morten Jensen