Commit Graph

11 Commits (521476a8d40922c20d1d422e3d3e093c6a5677e7)

Author SHA1 Message Date
Laszlo Nagy 94181206c2 jesd204/tb: Update testbenches 2021-02-05 15:24:15 +02:00
Matt Blanton 400c3927f7 jesd204: Add support for 8-byte JESD204B, frame alignment character insertion/replacement
Add support to JESD204 RX and TX core for 8-byte 8b/10b link mode,
and frame alignment character replace/insert with or without scrambling.
Add support for xcelium simulator to jesd204/tb
Increased cores minor version.
2021-02-05 15:24:15 +02:00
Matt Blanton 1e04b2e2f2 jesd204_rx: Add RX frame alignment character check
Add support for RX frame alignment character checking when scrambling is enabled and
for link reset on misalignment.
Add support for xcelium simulator to jesd204/tb
2020-07-31 11:43:41 +03:00
Laszlo Nagy c6c825c90a jesd204/tb: support for ModelSim and Xsim
Adding support for ModelSim and Vivado Xsim.

Usage:
  export SIMULATOR=modelsim
    or
  export SIMULATOR=xsim
2019-01-21 10:33:30 +02:00
Lars-Peter Clausen d72fac4b1e Add missing timescale annotations
For consistent simulation behavior it is recommended to annotate all source
files with a timescale. Add it to those where it is currently missing.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-10-17 10:32:47 +03:00
Lars-Peter Clausen 57a5baad33 jesd204: Fix loopback testbench
The loopback testbench currently fails, because the cfg_links_disable signal is not connected to the RX side of the link.

Fix this.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-07-24 15:20:28 +02:00
Istvan Csomortani 05dbe8f42f jesd204:tb: Update test bench to support dynamic multi-link on TX side 2018-05-03 19:37:35 +03:00
Istvan Csomortani bee392253b jesd204:tb: Fix the loopback_tb test bench
The jesd204_rx instantiation contained a port that did not exist. (phy_ready)
2018-03-28 15:19:18 +01:00
Lars-Peter Clausen 71cc052825 jesd204: rx: Use standalone counter for lane latency monitor
Use a single standalone counter that counts the number of beats since the
release of the SYNC~ signal, rather than re-using the LMFC counter plus a
dedicated multi-frame counter.

This is slightly simpler in terms of logic and also easier for software to
interpret the data.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-06-20 17:39:41 +02:00
Lars-Peter Clausen baa256e34c jesd204: Slightly rework sysref handling
For SYSREF handling there are now three possible modes.

1) Disabled. In this mode the LMFC is generated internally and all external
SYSREF edges are ignored. This mode should be used for subclass 0 when no
external sysref is available.
2) Continuous SYSREF. An external SYSREF signal is required and the LMFC is
aligned to the SYSREF signal. The SYSREF signal is continuously monitored
and if a edge unaligned to the previous edges is detected the LMFC is
re-aligned to the new edge.
3) Oneshot SYSREF. Oneshot SYSREF mode is similar to continuous SYSREF mode
except only the first edge is captured and all further edges are ignored,
re-alignment will not happen.

Both in continuous and oneshot signal at least one external sysref edge is
required before an LMFC is generated. All events that require an LMFC will
be delayed until a SYSREF edge has been captured. This is done to avoid
accidental re-alignment.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-06-20 17:39:41 +02:00
Lars-Peter Clausen 1202286c3d Add ADI JESD204 link layer cores
The ADI JESD204 link layer cores are a implementation of the JESD204 link
layer. They are responsible for handling the control signals (like SYNC and
SYSREF) and controlling the link state machine as well as performing
per-lane (de-)scrambling and character replacement.

Architecturally the cores are separated into two components.

1) Protocol processing cores (jesd204_rx, jesd204_tx). These cores take
care of the JESD204 protocol handling. They have configuration and status
ports that allows to configure their behaviour and monitor the current
state. The processing cores run entirely in the lane_rate/40 clock domain.

They have a upstream and a downstream port that accept and generate raw PHY
level data and transport level payload data (which is which depends on the
direction of the core).

2) Configuration interface cores (axi_jesd204_rx, axi_jesd204_tx). The
configuration interface cores provide a register map interface that allow
access to the to the configuration and status interfaces of the processing
cores. The configuration cores are responsible for implementing the clock
domain crossing between the lane_rate/40 and register map clock domain.

These new cores are compatible to all ADI converter products using the
JESD204 interface.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-23 11:16:07 +02:00