Commit Graph

10 Commits (537a284115eeb30b2d0031c6e7d453ab5496d39b)

Author SHA1 Message Date
stefan.raus 4a772265a9 Update Quartus Prime version from 19.3.0 to 20.1.0
adi_project_intel.tcl: Change quartus version to 20.1.0.
library: Set qsys version so that IP instances won't require a specific version.
2021-03-08 11:29:33 +02:00
Istvan Csomortani 0f7a3b953a scripts/adi_ip_intel: Rename the ad_alt_intf to ad_interface 2019-06-29 06:53:51 +03:00
Istvan Csomortani 5329458a62 library/scripts: Rename adi_ip_alt.tcl to adi_ip_intel.tcl 2019-06-29 06:53:51 +03:00
Laszlo Nagy 9273cde33f util_adcfifo/util_dacfifo: bundle AXIS signals into bus for Intel 2019-05-16 13:27:19 +03:00
Istvan Csomortani fa32ea8f1f util_dacfifo: Fix the reset logic of the module
Both the DMA and DAC side should be in reset at the positive edge of the
dma_xfer_req, so we can re-initialize the buffer.
2018-10-11 16:57:30 +03:00
Istvan Csomortani bdd7e29bae util_dacfifo: Integrate grey coder/decoder module
The grey coder/decoder function was limited to 10 bits, and this
resulted an unwanted limitation of the FIFO size. Using this
module, the coder/decoder data width can be adjusted to the current
address width.
2017-10-05 12:25:50 +01:00
Lars-Peter Clausen d7e87a60a9 Remove executable flag from non-executable files
All of these files are source code and are not executable standalone.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-28 17:56:07 +02:00
Rejeesh Kutty c728299e71 altera- default to latest version 2017-05-12 13:25:17 -04:00
Istvan Csomortani 760228d676 util_dacfifo: Update the util_dacfifo
Fix bypass and undate the general functionality. If bypass enabled
the FIFO will function as a normal CDC FIFO.
2017-03-03 18:43:36 +02:00
Rejeesh Kutty 104e9dfcdc adc/dac-fifo altera cores 2017-02-28 13:30:50 -05:00