Commit Graph

12 Commits (543e08b67ad28725fa8ffabb0e2ee90507f8562f)

Author SHA1 Message Date
Rejeesh Kutty e2f4a4c5cf library: make preset registered for timing paths 2015-06-10 13:41:41 -04:00
Rejeesh Kutty e7470036bf library- drp moved to up clock 2015-06-01 13:39:26 -04:00
Adrian Costina 83df53d9bf adc_common: Updated version because the delay registers have been changed 2015-05-25 17:18:14 +03:00
Rejeesh Kutty 6e047f78c6 delay-cntrl: up-clk, direct access + tx 2015-05-18 14:28:20 -04:00
Adrian Costina 1d26639d73 common: Added synchronization mechanism to the up_adc_common module 2014-10-22 10:05:55 +03:00
Rejeesh Kutty de33722470 up/constr: independent read/write and local constraints 2014-10-02 14:35:59 -04:00
Rejeesh Kutty 60dd14bcdb a5soc: removed jtag master control 2014-07-01 12:27:37 -04:00
Rejeesh Kutty b6052773b7 added adc/dac gpio registers 2014-06-27 14:45:58 -04:00
Rejeesh Kutty d4be46cc17 library: register map changes and for mathworks 2014-06-24 14:23:56 -04:00
Rejeesh Kutty ad491e92ab changed pcore version and made it local (top shouldn't override) 2014-03-14 12:02:16 -04:00
Rejeesh Kutty 23a62a92b2 up_adc_common: dma bus width is 0x8 (constant) 2014-03-06 19:22:19 -05:00
Rejeesh Kutty f7c9368abc initial checkin 2014-02-28 14:26:22 -05:00