6f2f2b8626
makefile: Regenerate make files
2021-01-20 01:02:56 +02:00
acbbd4636a
sysid: Upgrade framework, header/ip are now at 2/1.1.a
...
Unify tcl scripts; rename adi_pd_intel.tcl to adi_pd.tcl
add git branch to internal use area; update log prints;
update xilixn projects; fix cn0506 sysid script;
2021-01-20 01:02:56 +02:00
e41ba7f6f5
adrv9009zu11eg: Use adi_project_create instead of adi_project
2021-01-15 15:26:43 +02:00
2799777657
adrv9009zu11eg/adrv2crr_fmc: Fix hmc7044_car_gpio connections
2020-11-11 07:07:29 -05:00
ecd880d44c
adrv9009zu11eg:fmcomms8: Fix SPI timing constraint
2020-11-05 17:42:41 +02:00
ae7ec82334
adrv9009zu11eg: Update spi module to use generic verilog
2020-11-02 16:13:35 +02:00
9093a8c428
library: Move ad_iobuf to the common library, as it's not Xilinx specific
...
Updated all system_project and Makefiles
2020-11-02 16:13:35 +02:00
9364c8501a
adrv9009_zu11eg: Add synchronization at application layer
...
Switch RX path reset to be controlled by the TPL and use
RX SYSREF as external synchronization for the ADC TPL
Use TX SYSREF for synchornizing the TX DDS
2020-10-07 09:04:21 +03:00
d8ab27b2af
sysid: Remove cstring init string
2020-09-30 19:12:24 +03:00
c4b94fc564
adrv9009zu11eg: Add S JESD204 parameter for the projects
2020-02-18 11:19:02 +02:00
645696e5b4
adrv9009zu11eg: Extend SPI connection to the PL HD PINS expansion
2020-02-18 11:19:02 +02:00
d2817863a1
adrv9009zu11eg: Add FMCOMMS8 support
2020-02-18 11:19:02 +02:00
29f18e501e
adrv9009zu11eg: Cleanup bd file
2020-02-18 11:19:02 +02:00
74fc68d4c3
axi_fan_control: Changed temperature thresholds to registers
...
implemented mux for temp reading either from internal or external
source; updated regmap; added param to identify source for temp
information; updated tacho measurements; added AVG_POW param used
for tacho measuremet average useful for simulations; defaults for
tacho measurements changed to params and added registers; added
prescaler for fsm control, FSM updated; changed register write
process; connected INTERNAL_SYSMONE to regmap, value can now be
read by software;
2020-02-14 11:21:12 +02:00
09ad67bfd7
adrv9009zu11eg: Make the project more parametrizable
2019-12-04 14:59:18 +02:00
0cb5c0bdaf
adv9009zu11eg: Update FPGA to -2. Update DDR4 clock frequency
2019-11-27 16:27:44 +02:00
dfe3258a4f
adrv9009zu11eg: Add axi_sysid
2019-11-19 10:29:57 +02:00
81d3a9eb66
adrv9009zu11eg: Reduce SPI Clock speed to meet timing
2019-11-19 10:29:57 +02:00
a589a2c7eb
adrv9009_zu11eg_som: Change design partitioning
...
Create a structure similar with ADRV936x projects
2019-11-14 15:25:23 +02:00
Sergiu Arpadi
Istvan Csomortani
Adrian Costina