0644edb389
fmcomms8: a10soc: Move RX and Observation to second SDRAM interface
...
This is an attempt to get full bandwidth without a FIFO
2020-10-26 18:12:14 +02:00
3a5097875f
common: a10soc: Allow for the second SDRAM interface to be used at a different clock
2020-10-26 18:12:14 +02:00
6621fbec61
fmcomms8: a10soc: Initial commit
2020-10-26 18:12:14 +02:00
35e4eb6a7b
ad469x: Add reference design for ad469x eval board
2020-10-22 19:17:10 +03:00
83cebe899f
daq3: Update projects to the new TPL
...
Also modified the FIFO ports to have the same widths so that in a
future commit the bypass would be available for cases when the
sampling rate won't be the maximum rate or the number of channels
active will be less than maximum number of channels
2020-10-21 18:59:37 +03:00
9f58b465ea
adaq7980: Add AXI pulse generator to generate the offload trigger
2020-10-21 09:59:26 +03:00
37254358dd
makefile: Regenerate make files
2020-10-20 12:51:10 +03:00
1f6bba0aa1
ad77681: Add axi_clkgen ip for spi engine
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spi_clk changed from 40MHz to 80MHz
2020-10-19 10:42:21 +03:00
d6b23d5149
scripts/adi_pd_intel: Delete noisy print outs
2020-10-17 08:02:33 +03:00
66672932d5
adv7513/de10nano: Fix connection of ltc2308 SPI's interface
2020-10-14 10:37:14 +03:00
72635d73e3
cn0540: Add axi_clkgen to Makefile
2020-10-14 00:05:57 +03:00
9364c8501a
adrv9009_zu11eg: Add synchronization at application layer
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Switch RX path reset to be controlled by the TPL and use
RX SYSREF as external synchronization for the ADC TPL
Use TX SYSREF for synchornizing the TX DDS
2020-10-07 09:04:21 +03:00
4026eaa19b
ad9081_fmca_ebz: Fix device clocks termination
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The device clocks are AC coupled LVDS lines without external termination.
For proper operation internal differential termination must be enabled,
the DQS_BIAS will DC bias the AC coupled signal to VCCO/2 (1.8/2) 0.9V
2020-10-06 16:13:21 +03:00
1c208c01d6
ad9656:Add reference design for the ad9656 eval board ( #494 )
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Added reference design for the ad9656 evaluation board coupled with the
zcu102 carrier board. The JESD204 communication link that transfers data
from the 4 ADCs to the FPGA has the following paramenters : L=4, M=4, S=1,
F=2, HD=0, N=16, NP=16. The JESD204 line rate is configured to be 2.5GHz.
Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2020-10-06 09:53:40 +03:00
23cd6d2f91
sysid: Remove cstring init string
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These two projects were originally missed by the find/replace command
2020-10-02 23:34:40 +03:00
da6d9da4f0
projects: cn0540: coraz7s: Add XADC support
...
The coraz7s has an Arduino/chipKIT Shield connector with 6 Single-ended
and 8 Differential Analog inputs tied to Xilinx's XADC.
The CN0540 uses the A0-5 pins as single-ended ADC channels to monitor
the differential input, ADC driver, and buffer voltages.
Signed-off-by: Sergiu Cuciurean <sergiu.cuciurean@analog.com>
2020-10-02 11:14:21 +03:00
11822e2824
cn0540/coraz7s: Set and input delay of one spi_clk cycle for the MISO line
...
Note, the current SCLK to spi_clk ratio is four. That means, the input
delay in the MISO line is 25% of the SCLK period.
If the SCLK to spi_clk ratio is changing, this constraint must be
updated.
2020-10-02 10:50:06 +03:00
dae1de0405
cn0540/bd: Generate a 80MHz spi_clk
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Generate a higher frequency of spi_clk using an axi_clkgen. (MMCM)
CAUTION: ad7768-1 is still violating the standard SPI timing,
reducing the timing window significantly for the last bit (or last high
bit).
2020-10-02 10:50:06 +03:00
c656a2e29b
sysid: Initialize parameter
2020-09-30 19:12:24 +03:00
d8ab27b2af
sysid: Remove cstring init string
2020-09-30 19:12:24 +03:00
bd2126fd2f
cn0363: Remove iobuf for spi sdo
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iobuf was generating drc warning because it was not fully connected.
2020-09-25 16:40:41 +03:00
9c827d6b03
cn0540/de10nano: Ignore 15003 critical warning
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Ignore the following critical warning on DMAC instance:
Critical Warning (15003): "mixed_port_feed_through_mode" parameter of RAM atom
system_bd:i_system_bd|axi_dmac:axi_dmac_0|axi_dmac_transfer:i_transfer| \
dmac_request_arb:i_request_arb|dmac_dest_mm_axi:i_dest_dma_mm| \
altsyncram:bl_mem_rtl_0|altsyncram_0tp1:auto_generated|ram_block1a1
cannot have value "old" when different read and write clocks are used.
2020-09-25 12:56:53 +03:00
9cac38017b
daq2/a10soc: Set optimization mode to high performance effort
2020-09-25 12:56:14 +03:00
230c579339
common/s10soc: Input ports do not have a current strength property
2020-09-25 12:56:14 +03:00
5644907f75
adi_intel_msg: Dissable "unused TX/RX channel" critical warning for Stratix 10
2020-09-25 12:56:14 +03:00
a738879fa0
ad77681evb: Remove redundant ad_data_clk
2020-09-25 12:20:41 +03:00
144fcc2965
adrv9009: Fix typo for number of samples calculation for observation channel
2020-09-25 11:58:58 +03:00
bde2d1d66d
fmcomms8: zcu102: Leave the SPI constraint at 25 MHz
2020-09-25 11:54:12 +03:00
4d2e05d5dd
fmcomms8: common: In the SPI module, use ad_iobuf instead of a Xilinx primitive
2020-09-25 11:54:12 +03:00
f8c2eb12d4
fmcomms8: zcu102: Remove the test pins, as they are not connected
2020-09-25 11:54:12 +03:00
1e31b9dd97
arradio: Remove unused signals
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Remove 'ad9361_clk_out' since is not used anymore, fixing in this way 'Warning (21074): Design contains 1 input pin that do not drive logic'
2020-09-23 09:16:48 +03:00
f2f6422751
sysid: Fix board/project name underscore issue
2020-09-17 10:32:58 +03:00
6ae822d42c
cn0506_rmii: Fix no defined clock warnings
2020-09-16 10:57:15 +03:00
49d4286459
cn0540/de10nano: Delete GPIO connection to DRDY
2020-09-15 18:14:23 +03:00
4838ac0ac2
cn0540/coraz7s: Time the SPI interface of AD7768-1
2020-09-15 18:14:23 +03:00
0933949ad7
adv7513: Add initial project for de10nano
2020-09-15 18:14:23 +03:00
043ddbaf9f
cn0540: Add de10nano reference design
2020-09-15 18:14:23 +03:00
ad8d2d225f
de10: Delete redundant base design
2020-09-15 18:14:23 +03:00
fd1c3c7cdd
common/de10nano: Add de10nano base design
2020-09-15 18:14:23 +03:00
6cea8ce777
adi_project_intel: Add de10nano support
2020-09-15 18:14:23 +03:00
40772a8b2c
ad40xx_fmc/zed: Fix constraints, to avoid critical warnings in synthesis
2020-09-15 13:08:39 +03:00
3241924d14
sysid_intel: Added sysid to intel projects
2020-09-11 15:46:06 +03:00
f57643b451
sysid_intel: Added adi_pd_intel.tcl
2020-09-11 15:46:06 +03:00
0152b645a6
m2k: Fix Warnings
...
Fix warnings caused by attempting to set a value to a disabled parameter.
2020-09-11 10:23:26 +03:00
9ee0f09078
daq3:qsys: Activate input pipeline stage for AD9680's JESD interface
2020-09-09 14:15:37 +03:00
c8e0a1ec04
projects: adrv9009: intel: Update JESD204 LANE_RATE and REFCLK_FREQUENCY
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To match the Linux default setup.
Signed-off-by: Dragos Bogdan <dragos.bogdan@analog.com>
2020-09-09 14:15:37 +03:00
61ece1f1e9
s10soc: Insert an additional bridge between DMA and HPS
...
Due to the interface differences between HPS's AXI4 and DMA's AXI4, the
tool will try to automaticaly add some bridges between the two
interface. Unfortunatly it does generate timing issues at the f2sdram0
interface of the HPS instance. By explicitly instantiating an AXI
bridge, these timing issues disappears.
2020-09-09 14:15:37 +03:00
46b6bf8f8a
adrv9009/qsys: input pipline active for jesd204_rx and jesd204_rx_os
2020-09-09 14:15:37 +03:00
5a8f277253
adrv9009/s10soc: Add support for Stratix10 SOC
2020-09-09 14:15:37 +03:00
2b5136db98
scripts/project_intel.mk: Update CLEAN targets
2020-09-09 14:15:37 +03:00
eb8e1142cd
adrv9009/intel: Fix the register address layout
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The reconfiguration interface for the Stratix10 XCVR has a different
address width. Prepare the register map layout of the project to support
this new architecture.
2020-09-09 14:15:37 +03:00
8818089015
a10soc: Reconfiguration interface address width improvement
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The reconfiguration interface's address width is different in various
architectures. Define the required address width in system_qsys.tcl.
2020-09-09 14:15:37 +03:00
91b199a907
s10soc: Add new feature for ad_cpu_interconnect
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If we have a lot of peripherals connected to the CPU's memory interface,
the generated interconnect can grow to much decreasing the timing
margin.
One solution is to group the peripherals by its interface types and
functions and use bridges to connect them to the memory interface.
This commit adds the possibility to insert an Avalon Memory Mapped
bridge when we create the connection between the peripheral and CPU.
Should be used just with Avalaon Memory Mapped interfaces.
2020-09-09 14:15:37 +03:00
f9c4283f45
stratix10soc: Initial commit of base design
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Note: Currently we have a engineering sample version 2 board.
2020-09-09 14:15:37 +03:00
24090fafd8
adrv9001/zcu102: Loopback VADJ error to the FMC board
2020-08-31 14:14:03 +03:00
d14376547f
adrv9001/zed: Refactor VADJ test in VADJ error
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The ADRV9002 uses in the digital interface 1.8V, however the Zed VADJ is
selectable by a jumper can go up to 3.3V . Voltage levels higher than 1.8V
are detected by the EVAL-ADRV9002 board, asserting the VADJ_ERR pin.
If VADJ error is set high keep all drivers in high-z state and signalize
it to the software layer through a gpio line.
2020-08-31 14:14:03 +03:00
72f916fcf5
adrv9001/zcu102: Update interface signal names based on direction
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Let the names of signals from source synchronous interface match the
direction of the signals.
2020-08-28 13:23:00 +03:00
a212ad6e58
adrv9001/zed: Update interface signal names based on direction
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Let the names of signals from source synchronous interface match the
direction of the signals.
2020-08-28 13:23:00 +03:00
eb2f211d30
scripts/intel: Add message severity definition file
2020-08-25 14:46:52 +03:00
9c4df588bb
fmcomms2: a10soc remove project
...
Starting from Quartus 18.1 the project won't build as LVDS SERDES needs to be
driven by a dedicated reference clock pin and A10SOC doesn't have dedicated pins
routed at the _CC FMC location.
Prior to version 18.0 this was reported as a critical warning.
See https://community.intel.com/t5/Intel-Quartus-Prime-Software/LVDS-SERDES-reference-clock-enforcement-change-in-18-1/td-p/196078
2020-08-25 14:19:48 +03:00
118e1f9e8b
adrv9001/zed: Initial support for Zed
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CMOS only support for ADRV9001 on ZedBoard
2020-08-24 17:49:12 +03:00
b27f3ac18f
adrv9001:zcu102: Initial version
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Generic project that supports CMOS or LVDS interface for the ADRV9001 transceiver.
2020-08-24 17:49:12 +03:00
d8c98c9904
cn0540/coraz7s: Relax timing in SPI Engine
2020-08-24 16:45:02 +03:00
fa0b39fa20
adi_project_intel: Update QSYS generation
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In Quartus Prime in place of the set_domain_assignment command, the
set_interconnect_requirement command is used.
2020-08-17 12:02:49 +03:00
b54effc9c9
daq2/a10gx: Set optimization mode to aggressive performance
2020-08-17 10:43:03 +03:00
fb7da01498
adrv9371x/a10gx: Set optimization mode to aggressive performance
2020-08-17 10:43:03 +03:00
738f7af23b
ad40xx_fmc: SDI delay should be set to 1
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In general we have to add a delay of half SCLK cycle.
(latch the MISO on the next consecutive SCLK edge)
2020-08-13 10:01:16 +03:00
4766d01915
m2k: Update constraints
2020-08-13 07:01:19 +03:00
4d39a3595f
m2k: Connect signals for instrument sync
2020-08-13 07:01:19 +03:00
f3b69c15c9
scripts/intel: Update version check
2020-08-12 10:33:29 +03:00
218f45a0df
scripts/intel: Set supported Quartus version to 19.3
2020-08-12 10:33:29 +03:00
62eb5a067d
fmcomms2/a10soc: Unused outputs should be left hanging
2020-08-11 10:14:18 +03:00
a66029aef3
adrv9009/a10gx: Delete redundant timing constraints
2020-08-11 10:14:18 +03:00
02ada3bbf7
a10gx: Delete input/output delay definitions
...
All input and output delays should be referenced to a virtual clock.
If the input and output delays reference base clocks or PLL clocks rather than
virtual clocks, the intra- and inter-clock transfer clock uncertainties,
determined by derive_clock_uncertainty, are incorrectly applied to the I/O ports.
See mnl_timequest_cookbook.pdf for more info.
2020-08-11 10:14:18 +03:00
f1a0946a5d
daq3: Delete redundant timing constraint
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Delete none generic timing constarints related to the memory interface.
Set optimization mode to default.
2020-08-11 10:14:18 +03:00
1c907b9248
daq2/a10gx: Use the default optimization mode
2020-08-11 10:14:18 +03:00
9043f3737b
Revert "a10gx: Optimise the base design"
...
This reverts commit 9afc871b70
2020-08-11 10:14:18 +03:00
4af0c98c56
a10gx: Fix exceptionSlave interface definition for HPS
2020-08-11 10:14:18 +03:00
5ba3448987
scripts/project-intel: Update CLEAN target
2020-08-11 10:14:18 +03:00
0b51c474a1
a10gx: Add a Avalon Pipeline Bridge between EMIF and DMA's
2020-08-11 10:14:18 +03:00
6d19041b21
dac_fmc_ebz: QPRO is using apply_instance_preset
2020-08-11 10:14:18 +03:00
0de5039b96
avl_dacfifo: add_intance command must have a version attribute
2020-08-11 10:14:18 +03:00
8fd1ad64d6
quartus: Increase tool version to 19.2
2020-08-11 10:14:18 +03:00
f3142a6a7a
adi_project_intel: set_interconnect_requirment command is deprecated
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Use set_domain_assignment to set up the maximum pipeline stages for the
main interconnect.
2020-08-11 10:14:18 +03:00
a39fa831d0
ad9371:a10gx: Relax interconnect requirements
2020-08-11 10:14:18 +03:00
7e22f91429
adrv9371:a10gx: Remove constraint from DDR
2020-08-11 10:14:18 +03:00
359e5d94ec
a10gx: Remove constraint from eth_ref_clk
2020-08-11 10:14:18 +03:00
967a138d0f
adi_project_intel: Add support for Quartus Pro
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By defualt the supported tool chain is Quartus PRO. If you want to
build the project with Quartus Standard, you need to define an environment
variable called QUARTUS_PRO_ISUSED with the value 0. (e.g. export
QUARTUS_PRO_ISUSED=0 )
Note: Not all projects going to build on Quartus Standard, you should
fix the errors if there is any.
2020-08-11 10:14:18 +03:00
054193e083
adi_project_intel: Delete all MESSAGE_DISABLE assignment
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These kind of assignments should be placed into file like
~/projects/scripts/adi_xilinx_msg.tcl
2020-08-11 10:14:18 +03:00
4ca1311d57
quartus_pro: Global assignment ENABLE_ADVANCED_IO_TIMING is not supported
2020-08-11 10:14:18 +03:00
8d6b8fc631
Add cn0506_rmii/zcu102 support on revB
2020-08-10 18:32:44 +03:00
7e96514230
Add cn0506_rmii/zc706 support on revB
2020-08-10 18:32:44 +03:00
321b82398b
Add cn0506_rmii/zed support on revB
2020-08-10 18:32:44 +03:00
6c2b1b1634
fmcomms5/zc702: Fix the sys_dma_clk connections
2020-06-19 12:53:18 +03:00
137c31db1d
daq2/xilinx: Update project to use generic JESD204 TPL
2020-06-18 15:45:19 +03:00
299273f5a1
daq2/intel: Update project to use generic JESD204B TPL
2020-06-18 15:45:19 +03:00
847f0f22e6
cn0540: Fix typo
2020-06-04 18:38:14 +03:00
193fce338d
cn0540: Initial commit
2020-05-28 18:49:35 +03:00
03ab28d7bf
ad77681evb: Remove coraz7s project
2020-05-28 18:49:35 +03:00
71d500bdd4
adrv9009/intel: Use generic TPL cores
2020-05-26 16:22:30 +03:00
Adrian Costina
sergiu arpadi
Istvan Csomortani
Laszlo Nagy
hotoleanudan
Sergiu Cuciurean
Stanca Pop
stefan.raus
AndreiGrozav
Stanca.Pop
Dragos Bogdan