61afd106b5
util_clkdiv: Keep as valid only settings common for 7Series and Ultrascale
2017-01-18 11:56:24 +02:00
61ee24f26a
util_clkdiv: Make the clock division parametrizable and changed C_SIM_DEVICE to SIM_DEVICE
2017-01-16 14:37:26 +02:00
4b2602437f
util_clkdiv: Added Ultrascale support and switch to BUFGMUX_CTRL for glitch free switching
2017-01-13 13:54:07 +02:00
1f7d19688a
Update Makefile
2017-01-12 15:58:32 +02:00
b59549053c
scripts/adi_ip: Fix adi_ip_infer_interfaces process
...
This patch is a complementary fix of 8b8c37 patch. And fix
all the 'infer interface' issues.
The adi_ip_infer_interfaces process was renamed to
adi_ip_infer_streaming_interfaces. Now the process just do
what its name suggest.
Affected cores were axi_dmac, axi_spdif_rx, axi_spdif_tx, axi_i2s_adi
and axi_usb_fx3. All these cores scripts were updated.
2017-01-12 12:15:33 +02:00
9b29941c77
util_clkdiv: Add constraint file
2017-01-11 18:11:53 +02:00
c78c9cf633
util_fir_int: Updated coefficient file
2016-12-21 10:06:56 +02:00
c0a2ef1ac4
library- altera power up warnings
2016-12-20 16:18:15 -05:00
ce47cf8d30
ad_sysref_gen: Fix sysref generation
...
Toggle sysref output just if the sysref_en is asserted.
2016-12-19 18:02:49 +02:00
a228c05bd3
common: Add a SYSREF generation module
...
The SYSREF generator is using a simple free running counter,
which runs on the JESD204 core clock. The period can be
configured using a parameter, it must respect the constraints
defined by the JESD204 standard.
The generator can be enabled through a GPIO line.
2016-12-17 11:12:10 +02:00
596d0fa3fb
axi_ad9122: Add a constraint for a false path
2016-12-16 12:07:40 +00:00
a00d9870be
axi_ip_constr: Fix constraints
...
Modify a contraint for a false path, so it will be applied to
up_delay_cntr module too.
2016-12-16 12:01:38 +00:00
99f72a9b3b
util_gtlb: this core is obsoleted
...
The util_gtlb core is obsoleted by xilinx/axi_xcvrlb
2016-12-12 14:23:47 +02:00
5c8dde8483
util_jesd_gt: this core is obsoleted
...
The util_jesd_gt core is obsoleted by xilinx/util_adxcvr and altera/avl_adxcvr
2016-12-12 14:15:38 +02:00
8ebc8fe4e2
updated makefiles
2016-12-09 23:06:41 +02:00
854cd44026
ad9671- xcvr interface changes
2016-12-08 16:05:23 -05:00
977e6d9189
adi_ip_alt: Fix some typo
2016-12-06 15:24:21 +02:00
7876c8ffa4
axi_ad9684: Add loaden and phase ports for altera support
2016-12-06 15:24:20 +02:00
a7d3df8757
axi_ad9684: Update hw tcl script for altera
2016-12-06 15:24:20 +02:00
b0a5be8565
axi_ad9122: Add loaden port for altera support
2016-12-06 15:24:20 +02:00
cedca30cd6
axi_ad9122: Update hw tcl script for altera
2016-12-06 15:24:19 +02:00
0715c962f1
altera/ad_serdes: Fix net alignment for rx_out at ad_serdes_in
2016-12-06 15:24:19 +02:00
6cf9df50e3
altera/ad_serdes: Define DEVICE_FAMILY in hw script
2016-12-06 15:24:18 +02:00
8b8c37e2e2
scripts/adi_ip: Remove AXIMM inference from adi_ip_infer_interfaces
...
The AXI Memory Map interface is infered in the adi_ip_properties process.
Infer it again in the adi_ip_infer_interfaces brakes the flow,
the tool will not find the cell's address segment, so there will not be
any address space assigned to the AXI interface.
Affected cores were axi_i2s_adi and axi_spdif_tx.
2016-12-05 14:33:39 +02:00
753f4bd06e
axi_intr_monitor: Slightly modify counter start points
...
Start the counter_to_interrupt_cnt counter when the counter_to_interrupt
value is written to the register map. This gives applications better
control over when the counter starts counting.
Also start the counter_from_interrupt on the rising edge of the interrupt
signal to avoid bogus values.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-12-02 20:09:29 +01:00
334ce5ddc0
axi_intr_monitor: Fully register IRQ output signal
...
The IRQ signal goes to a asynchronous domain. In order to avoid glitches to
be observed in that domain make sure that the output signal is fully
registered.
This means that the IRQ signal is no longer mask when the control enable
bit is not set. Instead modify the code to clear the interrupt when the
control enable bit is not set. This turns it into a true reset for the
internal state.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-12-02 19:28:13 +01:00
170c781d02
hdlmake.pl- updates
2016-12-01 13:52:11 -05:00
95a2e02800
library/makefile- updates
2016-12-01 13:47:02 -05:00
609b01f9e4
util_clkdiv: Added division by 2 option
2016-11-24 16:01:37 +02:00
91ee4394e4
axi_intr_monitor: Initial commit
2016-11-24 15:19:36 +02:00
f03675cdab
axi_dmac: ID_WIDTH must be clog2(FIFO_SIZE*2)
2016-11-24 13:20:45 +02:00
c705623101
axi_dmac: Fix port connection and port width mismatch
2016-11-24 12:01:45 +02:00
862bd7ef2c
daq3/zc706- xcvr changes
2016-11-23 15:02:20 -05:00
025420d6f8
library/axi_xcvrlb- xcvr changes
2016-11-23 12:00:13 -05:00
8f562fd069
xcvr updates- board procedure
2016-11-22 14:43:36 -05:00
2ea997c3d5
interfaces- remove channel based pll reset
2016-11-22 11:34:29 -05:00
3dbed492b3
util_adxcvr: expose cpll/qpll as it is
2016-11-22 11:32:37 -05:00
3cbe735bd8
util_adxcvr: regenerate from script
2016-11-22 11:21:04 -05:00
c57ffc9364
axi_adxcvr- separate pll reset from channels
2016-11-22 11:12:54 -05:00
b9795c7033
xilinx/util_adxcvr: Update enablement dependencies
2016-11-22 17:33:40 +02:00
2f2570fcac
axi_i2s: Remove incorrectly inferred interfaces
...
Remove interfaces that were incorrectly inferred by the tools.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-11-18 15:01:29 +01:00
43c74bf55c
axi_i2s: Tie-off optional inputs
...
Tie-off all optional inputs to 0 so that they are driven to a defined value
when not used.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-11-18 15:01:26 +01:00
26907ef1fd
axi_i2s: Remove duplicated clock interface association
...
The I2S interface has a clock associated to it twice, this will generate a
critical warning when using the core, so remove one of them.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-11-18 15:01:24 +01:00
b85a282748
fmcomms11- lane swap
2016-11-16 10:26:47 -05:00
9d6c93a5d8
Fix warnings
2016-11-14 15:17:15 +02:00
12d6e46ae7
clean: Delete deprecated source files
...
The axi_jesd_gt was repleaced by axi_adxcvr IP, which is located
at library/xilinx and library/altera.
The axi_jesd_xcvr was an early version of axi_adxcvr.
The register map is moved to the IP's directory.
2016-11-14 10:43:46 +02:00
c80033cb1b
util_fir_int: removed s_axis_data_tvalid and updated sdrstk
2016-11-11 17:52:19 +02:00
6f4dc92dd2
util_fir_int: Fix channel data assignment
2016-11-11 15:46:17 +02:00
64d1d54ec0
util_fir_int: Update filter, as it's used with ad9361 in CMOS mode
2016-11-10 17:45:03 +02:00
66098b7ae7
util_fir_dec: Update filter, as it's used with ad9361 in CMOS mode
2016-11-10 17:43:04 +02:00
6073cdded4
axi_ad9250: Tie rx_valid to ground
2016-11-10 10:52:37 +02:00
8845aeb6ab
axi_ad9250: Add missing file to Make and script
2016-11-10 10:48:46 +02:00
8493bd4329
axi_ad6676: Update the core, sof interface added
2016-11-10 10:39:33 +02:00
0b58a2a1db
avl_adxcvr- sysclk frequency
2016-11-09 09:21:07 -05:00
48ee720901
avl_adxcvr- a5 requires single transceiver controller
2016-11-08 15:20:01 -05:00
a58597c13a
ad9250 - build fixes
2016-11-08 15:17:54 -05:00
d7357d781b
axi_ad9250 - avalon/axi streaming + sof
2016-11-04 15:30:39 -04:00
ee9c8b884d
avlxcvr- add arria v support
2016-11-04 15:01:19 -04:00
9dc7f16d80
axi_usb_fx3: Added zero length packet capability
2016-11-03 15:29:56 +02:00
1e0fed82f7
alt_serdes- a10 ddio fixes
2016-11-01 12:41:25 -04:00
5eff357568
up_tdd_cntrl: Fix memory map register writes
2016-11-01 10:06:57 +02:00
9f4c5f8060
arradio/ad9361- updates
2016-10-31 15:34:32 -04:00
b94cc8afb1
altera- cmos cores
2016-10-31 13:13:48 -04:00
e0459df0f3
altera -c5 qsys alternative
2016-10-31 11:18:27 -04:00
cc75fa3dfe
altera- java/tcl mess handling
2016-10-31 10:54:07 -04:00
a9d03af771
altera- serdes changes
2016-10-28 14:09:18 -04:00
f2e12cc88f
util_fir_dec: Shifted the output data to the left so that the amplitude remains
...
constant
2016-10-28 15:18:36 +03:00
d9b756e7ad
util_fir_int: Shifted the output data to the left so that the amplitude remains constant
2016-10-28 15:17:30 +03:00
30314e4492
library: Added util_fir_int and util_fir_dec interpolation/decimation filters
2016-10-27 19:31:50 +03:00
8107514dde
altera/common- ad_serdes_clk
2016-10-27 09:41:10 -04:00
f7e3703b98
axi_ad9371- avalon-s interfaces
2016-10-27 09:25:00 -04:00
6f611e0d10
altera/alt_serdes: Add support for Cyclone V
2016-10-25 20:32:51 +03:00
08cef5a745
axi_ad9361: Add Cyclone V SERDES support
2016-10-25 20:24:17 +03:00
5731ba3300
fmcomms11- xcvr updates
2016-10-24 09:51:40 -04:00
de0c487195
axi_ad9684: Add Altera support for the core
2016-10-24 11:43:22 +03:00
3f3606d318
axi_ad9122: Add Altera support for the core
2016-10-24 11:43:12 +03:00
aa46de5e5e
adi_ip_alt: Add ad_generate_module_inst proc
...
Add a tcl process, which can be used to generate custom module
names during the generation phase. This will be used to create
different ad_serdes_clk module, in case when independent IOPLLs are
needed for TX and RX.
2016-10-24 11:43:00 +03:00
707038937a
alt_serdes: Add additional parameters
...
Add additional parameters to keep the top of ad_serdes_* modules
consistant through differente carriers.
2016-10-24 11:42:43 +03:00
8dbfe9258f
axi_ad9162: Delete duplicated port
2016-10-21 13:47:01 +03:00
0beecea02d
util_adxcvr- ultrascale updates
2016-10-19 13:06:10 -04:00
72c05e8635
axi_dmac: Fix constraints for ultrascale
...
Replace "PRIMITIVE_SUBGROUP == flop" with "IS_SEQUENTIAL" as the former is
series7 specific while the later works on all platforms. This fixes the
axi_dmac timing constraints for ultrascale based platforms.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-10-19 14:00:54 +02:00
ecc0addb8c
scripts/adi_ip_alt.tcl: Script is case insensitive for its arguments
2016-10-18 11:25:06 +03:00
bf949f1a88
axi_xcvrlb- xcvr updates
2016-10-17 16:16:57 -04:00
1b3fcb5863
util_adxcvr- parameter defaults
2016-10-17 16:10:57 -04:00
a026d44435
axi_generic_adc: Add missing up_adc_common connections
2016-10-12 13:20:26 +03:00
b543402051
axi_mc_current_monitor: Add missing up_axi connection
2016-10-12 13:20:26 +03:00
91995c082d
axi_ad9684: Fixed up_drp_*data width
2016-10-12 13:20:26 +03:00
a505d304af
Add up_dac_common missing connections
2016-10-12 13:20:26 +03:00
43ee917d53
Add up_dac_channel missing connections
2016-10-12 13:20:26 +03:00
1131be91ed
axi_ad9361: Makefile update
2016-10-11 23:34:13 +03:00
b7767aa18f
xilinx/axi_ad9361_lvds_if: Remove ila
2016-10-11 18:13:45 +03:00
2d93d787ab
altera/ad_cdfilter: Update interface to Verilog 2001 standard
2016-10-11 17:59:21 +03:00
369dad60b0
axi_ad9361: Add Altera SERDES interface support
2016-10-11 17:59:19 +03:00
ae47895666
altera/alt_serdes: Fixed SERDES 4 factor initialization
2016-10-11 17:59:17 +03:00
d41945f568
altera/ad_serdes: Add support for any SERDES factor less than 8
2016-10-11 17:59:14 +03:00
52194f0fea
axi_ad9361: Add DRP connection to the interface module
2016-10-11 17:59:12 +03:00
7194d2eccc
axi_ad9361: Grup interfaces to add support for more carriers
2016-10-11 17:58:49 +03:00
cc6ca4f0f2
ad_lvds_in- ultrascale sim device
2016-10-10 10:39:47 -04:00
121b341b45
axi_spdif_rx: Fixed version register issue. Added sampled_data to sensitivity list
2016-10-10 17:30:13 +03:00
ff980551e6
ad_serdes: SERDES_FACTOR handover missing
...
In modules ad_serdes_in/ad_serdes_out the handover of the parameter
SERDES_FACTOR did not exist, causing unwanted behavioral in case of
factors less than 8.
SERDES_FACTOR must be hand over to DATA_WIDTH parameter of the SERDES
primitive.
2016-10-10 16:38:42 +03:00
Adrian Costina
Istvan Csomortani
Rejeesh Kutty
Lars-Peter Clausen
AndreiGrozav