566e8d7fd3
makefile: added
2015-04-01 16:27:47 -04:00
500f71af2f
makefile: added
2015-04-01 16:27:46 -04:00
4e7538fc8b
makefile: added
2015-04-01 16:27:45 -04:00
13a40af558
makefile: added
2015-04-01 16:27:44 -04:00
36b629dab1
makefile: added
2015-04-01 16:27:42 -04:00
856220e9e9
makefile: added
2015-04-01 16:27:41 -04:00
43f5025ecd
makefile: added
2015-04-01 16:27:40 -04:00
5b18d12c23
makefile: added
2015-04-01 16:27:39 -04:00
f20ab424f7
makefile: added
2015-04-01 16:27:37 -04:00
4ab17615ce
makefile: added
2015-04-01 16:27:36 -04:00
234d4ae7f3
makefile: added
2015-04-01 16:27:35 -04:00
55406b7a61
makefile: added
2015-04-01 16:27:34 -04:00
6cff03390c
makefile: added
2015-04-01 16:27:32 -04:00
a97fc603f8
makefile: added
2015-04-01 16:27:31 -04:00
35205c43a1
makefile: added
2015-04-01 16:27:30 -04:00
1b5737968a
makefile: added
2015-04-01 16:27:29 -04:00
6ac43fe516
makefile: added
2015-04-01 16:27:27 -04:00
c2e626d0b6
axi_hdmi_tx: es split
2015-04-01 15:08:24 -04:00
3bca324c33
hdmi_rx: 64bit + es split
2015-04-01 14:25:55 -04:00
56165b89f7
hdmi_rx: 64bit + es split
2015-04-01 14:25:49 -04:00
01d0b495ec
hdmi_rx: 64bit + es split
2015-04-01 14:25:45 -04:00
d4763fe356
hdmi_rx: 64bit + es split
2015-04-01 14:25:41 -04:00
11d94b736a
util_gmii_to_rgmii: Added to dev branch
2015-04-01 17:22:49 +03:00
ae26c7817e
Remove util_sync_reset
...
The util_sync_reset peripheral hasn't been used in a while and will not be
used in new projects. So remove it.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-01 14:46:41 +02:00
fd7a423f74
axi_dmac: Reset data stream resize blocks when disabled
...
When the DMA controller gets disabled in the middle of a transfer it is
possible that the resize block contains a partial sample. Starting the next
transfer the partial sample will appear the begining of the new stream and
also cause a channel shift.
To avoid this make sure to reset and flush the resize blocks when the DMA
controller is disabled.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-01 14:18:34 +02:00
2d7bae2ba6
axi_mc_controller: Added delay module
2015-04-01 12:22:20 +03:00
de12184038
axi_mc_speed: Updated for motor control revision 2
2015-04-01 11:43:22 +03:00
d5fa0071bd
axi_mc_current_monitor: Updated for motor control revision 2
2015-04-01 11:42:28 +03:00
6ee66df41e
axi_mc_controller: Updated for motor control revision 2
2015-04-01 11:41:33 +03:00
4b1d9fc86b
axi_dmac: Modified in order to avoid vivado crash
2015-04-01 11:39:25 +03:00
e116822059
imageon_zc706: Updates and fixes
...
+ sync the sof to the dma_de signal
+ hdmi_rx_dma is connected to the HP1
+ fix syncronization signal in the CSC module
+ hdmi_rx_clk is asynchronous
2015-03-27 18:57:32 +02:00
0e1a60e8b7
axi_dmac: Brought up the transfer request signal for the dest_fifo and dest_axi_stream interface.
2015-03-26 12:20:32 +02:00
6ee9b3a1e2
util_wfifo: Fixed reset
2015-03-25 15:34:21 +02:00
552d9b41f7
imageon: updates
2015-03-24 15:08:48 -04:00
b29e97f985
hdmi_rx: imageon updates
2015-03-24 15:08:48 -04:00
ffe410b2dd
hdmi_rx: imageon updates
2015-03-24 15:08:48 -04:00
09bb184505
hdmi_rx: imageon updates
2015-03-24 15:08:48 -04:00
f92011f72d
hdmi_rx: imageon updates
2015-03-24 15:08:48 -04:00
5d50d38c66
hdmi_rx: imageon updates
2015-03-24 15:08:48 -04:00
80c2a5a45d
axi_hdmi_rx: General clean up
2015-03-23 12:39:26 +02:00
8f5551718e
axi_fifo2s: false paths on up_xfer_toggle
2015-03-19 16:33:14 -04:00
7e15fd9e5b
util_upack: Fixed ip
2015-03-19 16:22:12 +02:00
bc04e5a4ce
axi_i2s_adi: Fixed pins directions
2015-03-12 17:22:52 +02:00
8dfcbdfd48
gt_channel/gt_common: simulation parameter warning fix
2015-03-06 12:36:07 -05:00
57e1f0e334
gt_channel/gt_common: simulation parameter warning fix
2015-03-06 12:36:03 -05:00
2d01955042
up_gt: change version dfe/lpm support
2015-03-05 09:47:16 -05:00
6995f63134
Add version check to adi_ip.tcl too.
2015-03-05 11:55:09 +02:00
1613f7fb41
cftl_cip: Add util_pmod_fmeter IP to library
...
Frequency meter IP for CN0332.
2015-02-23 17:20:12 +02:00
65bda6505e
axi_dmac: Correctly handle shutdown for the request splitter
...
We need to make sure to not prematurely de-assert the s_valid signal for the
request splitter when disabling the DMAC. Otherwise it is possible that
under certain conditions the DMAC is disabled with a partially accepted
request and when it is enabled again it will continue in an inconsistent
state which can lead to transfer corruption or pipeline stalls.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-02-19 17:22:23 +01:00
731e1c0996
axi_dmac: Use internal enable signal for the request generator
...
All components should use the internal 'do_enable' signal instead of the
external 'enable' signal. The former correctly incorporates the shutdown
sequence and does not get asserted again until the shutdown has been
completed. Using the external signal can cause problems when it is disabled
and enabled again in close proximity.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-02-19 17:22:23 +01:00
Rejeesh Kutty
Adrian Costina
Lars-Peter Clausen
Istvan Csomortani