68461110aa
Replace link in license header from master to main
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Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2024-01-16 16:48:45 +02:00
c9a7d4d927
Add copyright and license to .tcl, .ttcl files
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Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-25 15:22:26 +03:00
28c06d505f
Add/edit copyright and license for .v, .sv files
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Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-11 15:17:41 +03:00
72378a6d4a
projects: Add fmc connection files for eval boards
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Creating a new eval board fmc file:
- docs: Open FMC_eval_board_template.xlsx
- follow the instructions on the first sheet
2022-09-20 14:11:08 +03:00
158c10df34
projects: starndadize the jesd make parameters
2022-09-13 11:53:21 +03:00
961ebe0cc2
projects: Update .v files according to guideline
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Deleted lines after endmodule and consecutive empty lines.
Modified parentheses, extra spaces.
Fixed indentation.
Fixed parameters list to be each parameter on its line.
Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-06-28 18:06:56 +03:00
69839ec327
ad_quadmxfe1_ebz: Refactor MxFE GPIOs
2022-05-11 18:09:08 +03:00
53a95840c0
ad_quadmxfe1_ebz_bd: Bugfix for JESD configurations with less lanes
2022-05-09 10:43:31 +03:00
aa1192a9bc
ad_quadmxfe1_ebz_bd: Connecting all the unused lanes in util_xcvr
2022-03-23 08:13:09 +02:00
7702079af5
ad_quadmxfe1_ebz: Fix external sync for ADC path
2022-02-08 16:56:01 +02:00
1cd866445e
ad_quadmxfe1_ebz: Initial version
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Parametrizable project for the QUAD-MxFE platform ADQUADMXFE1EBZ,
ADQUADMXFE2EBZ, ADQUADMXFE3EBZ
Default mode set to:
TX JESD204C MODE 11, M=16, L=4
RX JESD204C MODE 4, M=8, L=2
For 204C 64B66B mode as physical layer the Xilinx Phy is uesd.
2021-11-10 14:03:34 +02:00
Iulia Moldovan
AndrDragomir
LIacob106
Laszlo Nagy
Filip Gherman