Istvan Csomortani
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dd7bac41c1
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daq1 : Update project to 2014.2
- Cores are upadted
- Concat module does not swap output anymore
- Clock signal name ps7_clk_* changed to clk_fpga_*
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2014-09-22 17:33:50 +03:00 |
Adrian Costina
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a49eb5853b
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ZED, ZC702: Added contraints so that projects can successfully synthesize on linux systems
For ZC706 Fixed one constraint which was not correct
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2014-08-26 16:28:41 +03:00 |
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Adrian Costina
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6c6cab0e16
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fmcomms2: ZC706 modified constraints for linux build machines
The added constraints allow the project to successfully pass timing on some ubuntu or debian build machines.
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2014-08-01 17:34:36 +03:00 |
Rejeesh Kutty
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ddac1a8834
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added common board files
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2014-02-28 21:17:01 -05:00 |