Adrian Costina
c19749361d
Makefiles: Updated makefiles to have as a result the programming file instead of the project file.
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Also fixed altera projects dependencies
2015-05-18 17:22:46 +03:00
Adrian Costina
949abcdc8f
Makefile: Updated makefiles so that the project recipe does not depend on lib
2015-05-06 14:58:29 +03:00
Lars-Peter Clausen
bd6c76f4ab
fmcomms5: Set DMA AXI type to AXI3 on ZYNQ
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The HP memory ports on ZYNQ are AXI3. The AXI-DMAC supports both native AXI3
and AXI4, by configuring it for AXI3 there is no need for a protocol
converter inside the interconnect, that connects the DMAC to the HP port.
In addition to that also set the data width for the DMAC on the HP port side
to 64 so there is no need for a memory width converter in the interconnect.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-23 14:33:47 +02:00
Adrian Costina
dc2b37bd0c
Makefile: Added top level Makefile. Modified behavior of clean and clean-all
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Clean ran for a project will clean only the project files.
Clean-all ran for a project will clean also the library files on which the project depends.
The clean commands will only remove specific files and directories.
The top Makefile allows several options(per suggestion from jameyhicks):
make fmcomms1.zed will run "make all" in projects/fmcomms1/zed/
make clean will run "make clean" for all the projects
make clean-all will run "make clean" for all the projects and libraries
make lib will run "make all" for the library files
2015-04-17 17:22:38 +03:00
Adrian Costina
780455d68c
Makefile: Updated makefiles. Added makefiles for altera
2015-04-09 17:57:06 +03:00
Rejeesh Kutty
5f8e9a74ea
makefile: updated
2015-04-07 16:32:01 -04:00
Adrian Costina
f79a152958
Makefiles: updated all makefiles adding clean functionality
2015-04-03 11:57:54 +03:00
Adrian Costina
51b5e4ddc5
fmcomms5: Moved the clock generation for dma transfer inside system_bd of the platform
2015-04-02 22:29:17 +03:00
Rejeesh Kutty
59698474af
makefile: added
2015-04-01 16:29:49 -04:00
Rejeesh Kutty
596d9db915
makefile: added
2015-04-01 16:29:48 -04:00
Rejeesh Kutty
968836011f
makefile: added
2015-04-01 16:29:47 -04:00
Adrian Costina
e58e9bc701
fmcomms5: Updated zc702 project to the latest framework
2015-03-31 17:44:09 +03:00
Adrian Costina
fb3ee53790
fmcomm5: Updated ZC706 project
2015-03-31 17:43:30 +03:00
Adrian Costina
92aa58826d
fmcomms5: Updated project to be compatible with both ZC702 and ZC706
2015-03-31 17:42:44 +03:00
Adrian Costina
1828a94446
fmcomms5: Updated common and ZC706 project to the latest framework
2015-03-25 17:42:11 +02:00
Adrian Costina
0ade2a5f67
fmcomms5: Updated project to vivado 2014.2. Updated interrupt system. Fixed constraints
2014-11-07 13:45:15 +02:00
Istvan Csomortani
17675863e0
all_projects: Fix the interrupt connections to preserve IRQ layout
2014-10-22 11:48:08 +03:00
Adrian Costina
a49eb5853b
ZED, ZC702: Added contraints so that projects can successfully synthesize on linux systems
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For ZC706 Fixed one constraint which was not correct
2014-08-26 16:28:41 +03:00
Adrian Costina
e9f8c0fb5f
fmcomms5: ZC706 modified constraints for linux build machines
2014-08-01 18:09:55 +03:00
Adrian Costina
9cdd4107cd
fmcomms5: ZC702: add reset_b and fixed system_top
2014-07-25 15:24:11 +03:00
Adrian Costina
7000897031
fmcomms2, fmcomms5: updated util_adc_pack and util_dac_unpack
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The cores now support up to 8 channels, in 1, 2, 4, 8 channel active configuration
2014-07-24 19:57:22 +03:00
Adrian Costina
a68f634de9
fmcomms5: Added resetb for the second AD9361
2014-07-24 17:31:30 +03:00
Rejeesh Kutty
b434fe6dd5
fmcomms5: register map changes
2014-07-08 16:57:43 -04:00
Rejeesh Kutty
bab90a19c2
fmcomms5/zc702: removed unused ila cores
2014-05-20 14:42:48 -04:00
Rejeesh Kutty
7e6b4ea9d0
fmcomms5: ignore only common clock to external clocks
2014-05-19 20:38:41 -04:00
Rejeesh Kutty
9a36075324
moved fmcomms5
2014-05-19 13:49:49 -04:00