6197a82c80
fmcomms2/common: Add the util_tdd_sync module
2015-11-11 11:07:15 +02:00
fc0f4bc414
axi_ad9361: Delete the old sync generator from the core
...
+ Define two control signal for util_tdd_sync : tdd_sync_en and tdd_terminal_type
+ Delete to old ad_tdd_sync.v instances from the core
+ Update Make files
+ Update ad_tdd_control: add additional CDC logic for tdd_sync (the sync comes from another clock domain)
+ Update the ad_tdd_sync module: it's just a simple pulse generator, the pulse period is defined using a parameter, pulse width is fixed: 128 x clock cycle
+ Update TDD regmap: tdd sync period is no longer software defined
2015-11-11 11:06:19 +02:00
a290611c09
util_tdd_sync: Initial commit
...
A synchronization signal generator for AD9361 running on TDD mode.
If the associated device is master, the module generates a pulse in a defined interval. Otherwise receives the sync signal from outside.
2015-11-11 10:46:11 +02:00
5cc97c78d3
Makefiles: Update makefiles to include the nerw axi_gpreg / util_mfifo libraries
2015-11-10 09:32:50 +02:00
ef9bdf6ec9
adi_project: Regenerate the layout of the IP Integrator subsystem design.
2015-11-09 11:01:10 +02:00
1d6254fdec
pzsdr/ccbrk: loopback board support
2015-11-06 11:34:21 -05:00
e7fd964874
axi_clkgen: Added a second input clock option
2015-11-06 17:55:29 +02:00
afc4274ee3
common scripts: Changed the resulting hdf file to system_top_bad_timing, if design doesn't meet timing.
2015-11-06 16:01:19 +02:00
0c7c0f2cd8
common scripts: Change the name of the generated HDF if the design doesn't meet timing
2015-11-05 18:41:51 +02:00
11718291cf
pzsdr/ccfmc- add single loopback core
2015-11-05 11:28:38 -05:00
839e76996f
axi_gpreg: added constraints
2015-11-05 11:28:37 -05:00
482b740229
axi_gpreg: add buffer enable
2015-11-05 11:28:35 -05:00
66d4f8fd58
util_gtlb: output receive/transmit clocks
2015-11-05 11:28:34 -05:00
9e27a60478
pzsdr/ccfmc- single loopback core
2015-11-05 11:28:33 -05:00
28bfeb442c
util_gtlb- syntax error fixes
2015-11-05 11:28:31 -05:00
e36f27b061
daq2: Update A10GX project, with the latest changes.
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Works with up to 64k samples
2015-11-04 14:54:09 +02:00
83399ef6ee
a10gx: Updated common project to work with Linux (enabled MMU)
2015-11-04 13:35:52 +02:00
6d28a92b5b
util_adcfifo: Added altera initial constraints file
2015-11-04 13:34:52 +02:00
e8b84b3662
axi_dmac: Updated axis destination / source ports for altera component
2015-11-04 13:33:41 +02:00
de53a61902
util_adcfifo: Put a limit on the read/write address from memory so there is no overflow
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Added altera component
2015-11-04 13:31:50 +02:00
6cfc13a9dd
common: Allow for the memory to be also symetrical
2015-11-04 13:28:02 +02:00
ad1cef1441
axi_gpreg: compile fixes
2015-11-03 14:29:00 -05:00
c8019b69fd
axi_gpreg- added
2015-11-03 14:28:59 -05:00
88f247a1de
util_gtlb: use gpio
2015-11-03 14:28:57 -05:00
a0039ed4fe
ccfmc: Launch HDMI data on falling edge
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The ADV7511 captures data on the rising edge, so make sure to launch data
on the falling edge. This fixes some issues with image stability.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-11-03 10:59:13 +01:00
acd9efc528
axi_hdmi_tx: Add parameter to configure the output clock polarity
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In order to maximize the window where it is safe to capture data we ideally
want to launch data on the opposite edge to which it is captured. Since the
edge on which data is captured depends on the connected device add a
parameter that allows to configure the launching edge.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-11-03 10:59:13 +01:00
6dddac5d94
ccfmc- missing board io
2015-11-02 15:45:14 -05:00
cafc80c829
fmcadc5: add programmable io delay
2015-11-02 12:10:18 -05:00
8b95520767
pzsdr/ccfmc- add loopback gpio/gt cores
2015-10-30 18:48:26 -04:00
88568c21e1
util_gtlb: updates for latest axi_jesd_gt
2015-10-30 18:47:36 -04:00
92b7570864
pzsdr/ccfmc- add ad9517 signals
2015-10-30 10:50:53 -04:00
b3cb84cf91
fmcadc5- added ila
2015-10-29 16:48:21 -04:00
24d76c610a
fmcadc5- fix core connections
2015-10-29 16:47:56 -04:00
ac4091e19e
fmcadc4- add monitor fifo
2015-10-27 14:52:02 -04:00
2b6ae00a44
library: add mfifo
2015-10-27 14:52:02 -04:00
b5d3d0bd13
usb_fx3: Added axi_usb_fx3 core and DMA to the project
2015-10-27 09:41:18 +02:00
748a2bc87a
fmcadc4- add ila for zc706 only
2015-10-23 14:32:35 -04:00
b2d0f5c56e
fmcadc4- use the same source/name for clocks
2015-10-23 14:32:35 -04:00
f1ed27105f
library/common- reset fix
2015-10-23 14:32:35 -04:00
32b3cfd8b9
axi_usb_fx3: Initial commit of the core with interface stub
2015-10-23 13:27:00 +03:00
9d2b8809df
Makefiles: Updated Makefiles
2015-10-23 10:44:27 +03:00
cb2bda48c0
fmcadc5- gt/ip updates
2015-10-19 09:31:32 -04:00
ed918ec119
imageon - keeping scripts happy
2015-10-16 15:04:02 -04:00
e14e9294c5
project-names -- variables causes scripts to fail- too much parsing
2015-10-16 14:13:56 -04:00
36dd6427fe
pzsdr: Add untracked Makefiles
2015-10-16 13:58:36 +03:00
6fb56079ee
library/util_gtlb: Add Makefile
2015-10-16 13:58:01 +03:00
8ecdb4a4ca
library/tdd_control: Add common registers to the register map and fix init value of a register
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+ Software in general needs to have access to the VERSION register.
+ tdd_sync_d3 registers init value should be 1'b0
2015-10-16 11:57:54 +03:00
bbdc693954
pzsdr/all: Update Makefile
2015-10-16 11:57:51 +03:00
44568f1f64
util_jesd_gt: bad idea, it is needed for ipi
2015-10-15 11:13:08 -04:00
08777ca566
fmcadc5- latest board changes
2015-10-15 10:46:07 -04:00
Istvan Csomortani
Adrian Costina
Rejeesh Kutty
Lars-Peter Clausen