Rejeesh Kutty
|
b55d0d7ad1
|
a5soc: constraints for false paths
|
2014-04-30 16:14:30 -04:00 |
|
Rejeesh Kutty
|
0b1ce14842
|
a5soc: basic hardware build
|
2014-04-30 12:40:27 -04:00 |
|
Rejeesh Kutty
|
99d66e7580
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a5soc: initial-copy version
|
2014-04-30 12:40:26 -04:00 |
|
Rejeesh Kutty
|
33979fc533
|
fixes to improve timing - fifo for clock domain transfers
|
2014-04-04 13:49:53 -04:00 |
|
Rejeesh Kutty
|
6a19b34a00
|
a5gt: added tightly coupled memory
|
2014-04-03 20:50:17 -04:00 |
|
Rejeesh Kutty
|
12e5cc91bd
|
make signaltap/timing part of the flow
|
2014-04-03 20:50:15 -04:00 |
|
Rejeesh Kutty
|
e85153b5dd
|
altera hal version
|
2014-04-01 21:12:11 -04:00 |
|
Rejeesh Kutty
|
04df908fbf
|
altera-fmcjesdadc1 initial checkin
|
2014-04-01 12:01:57 -04:00 |
|
Rejeesh Kutty
|
0d678b89ed
|
altera a5gt fmcjesdadc1 setup
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2014-04-01 11:46:37 -04:00 |