Unified the ad7606x_fmc project, where both the serial and the parallel interface are implemented.
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Signed-off-by: Ioan-daniel Pop <Pop.Ioan-daniel@analog.com>
1. Add intermediary data_src_select register to control output selection
between DMA and RAW. The switch RAW->DMA is not made until DMA has valid
data; the switch DMA->RAW is not made until overwrite_enable is 1
regardless of dac_valid.
2. When overwrite is enabled, set the intermediary DMA register data_r
to the RAW value.
This fixes an issue of the logic analizer that caused the last sample of a DMA
transfer to be visible at the next DMA transfer.
Signed-off-by: dumitruceclan <dumitru.ceclan@analog.com>
This change will fix the timing closure for designs where the external
clock is not a submultiple of the s_axi_clk.
Signed-off-by: AndreiGrozav <andrei.grozav@analog.com>
New features:
1. External sync force the phase align. The external sync was used to align
the phases of enabled pwms, but only after being armed by a
load_config signal toggle.
This feature lets the user decide between using load_config to
arm and wait for a neg-edge of sync or automatic phase align trigger
on the ext_sync neg-edge.
2. Force align. Lets the user chose between immediately stopping the
active pulses and realigning them, or waiting for all running pulse
periods end, before realigning.
3. Start at sync. When this feature is activated, the pulses will start immediately
after the trigger event. Otherwise, each pulse will start after a period
equal to the one for which it is set.
4. Use parameters to set the default status after reset of the
- soft reset
- start at sync
- force align
- ext sync align
Update regmap.
Fixes:
1. The polarity on disabled channels was staying high instead of low.
2. Fix 0 and 100 proc duty cycle configuration.
Signed-off-by: AndreiGrozav <andrei.grozav@analog.com>
Signed-off-by: Alin-Tudor Sferle <Alin-Tudor.Sferle@analog.com>
Intermittently DAC channel data is 0 after multiple new buffers.
Due to the low sampling rate and DMA flushing, it happens that the
transfer SM gets stuck in flushing mode right before the transmission
should start.
Another frequent issue happens when a new transmission is started.
A buffer must be pushed independently for each channel because of
separate DMAs.
After the first buffer is pushed the Linux driver deactivates the
start_sync flag. Not knowing if the other channel/buffer will be
active/pushed. The start_sync will be re-enabled with the second buffer.
The issue was that the SM of the first buffer went one step further
before the push if the second buffer,not being stopped by the
start_sync.
Signed-off-by: AndreiGrozav <andrei.grozav@analog.com>
Add I3C Controller IP with required I3C features support.
Uses IRQ based DAA.
Supports speeds at 100MHz clk: 12.50MHz, 6.25MHz, 3.12MHz, 1.56MHz
Basic IBI support with/without MDB.
Compatible with AMD Xilinx and Altera FPGAs.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
With the new make -jX support flock is used but shells out sometimes.
This assumes a bash like shell which isn't always the case. This fix
forces flock to use sh.
Signed-off-by: Travis F. Collins <travis.collins@analog.com>
Lattice tools give error for using blocking assignments at one side
and non blocking in the other.
Signed-off-by: Villyam <Vilmoscsaba.Jozsa@analog.com>
docs: Add JESD204 documentation in sphinx
Fixes several semantic issues from the original doc in wiki
Implicit path to library when the doc is hierarchically coherent with the
library.
Signed-off-by: Carlos Souza <carlos.souza@analog.com>
Co-authored-by: Jorge Marques <jorge.marques@analog.com>
Revert AXI bus signals back to upper case on SPI Engine Offload IP,
changed on e2ca5a991a.
Fixup signals from sd*_data_* to sd*_* for spi_engine_ctrl interface.
Non-breaking mistake, but added warnings to the IP.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
* SPI Engine: Add registers for Offload memory and FIFO sizes
Adds registers at dword 0x04 and 0x05, respectively allowing software
to get the sizes of the Offload Module memories (command and sdo) or
the sizes of the FIFOs on the AXI regmap.
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
* AD7768_zed: Fix wideband filter bug
In SPI control mode, when not used as GPIO the FILTER pin and when a
crystal is used as the clock source, this pin must be set to 1.
The START pin must be tied to a logic 1 through a pull-up resistor, when
it is not used.
Use tcl script instead of static xmls for the interface.
Easier to maintain and are not gitignored.
Rename spi_master to spi_engine because every interface should be
prefixed by the IP name; in this case, spi_engine.
Also, remove interface/*.sv files on make clean and git ignore them.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
The extensions have been moved to docs tools.
The source code is available at
https://github.com/analogdevicesinc/doctools
And is installed as before:
(cd docs ; pip install -r requirements.txt --upgrade)
Since the package is listed on the requirements.txt file.
Also, add index for library and projects
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
* Value 24 was wrongfully set for parameter LENGTH_WIDTH, because
it is not among the valid values, which are 28, 29, ..., 34. Set '28'
to be the default value
* Vivado Tcl somehow didn't accept the old expression set for
calculating the HBM_SEGMENTS_PER_MASTER parameter, so it was changed
accordingly to work. Dropped "expr", ".0" and "int ()" parsing and now
it works
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
The introduction of sysid IPs on some Stratix 10 projects introduced a
problem where they would fail to build, due to mem_init_sys_file_path
not being defined. This is fixed now.
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
* SPI Engine: fix early sdi data clear
In case an SPI read was immediately followed by a cs assert, the sdi
register was being cleared one cycle too soon, so that the data being
passed on was always 'b0.
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
PIoandan
AndreiGrozav
dumitruceclan
Iulia Moldovan
Jorge Marques
Jorge Marques
IstvanZsSzekely
ladace
Villyam
Stanca Pop
caosjr
Alin-Tudor Sferle
Sergiu Arpadi
LBFFilho
AndrDragomir
laurent-19