Unified the ad7606x_fmc project, where both the serial and the parallel interface are implemented.
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Signed-off-by: Ioan-daniel Pop <Pop.Ioan-daniel@analog.com>
With the new make -jX support flock is used but shells out sometimes.
This assumes a bash like shell which isn't always the case. This fix
forces flock to use sh.
Signed-off-by: Travis F. Collins <travis.collins@analog.com>
* AD7768_zed: Fix wideband filter bug
In SPI control mode, when not used as GPIO the FILTER pin and when a
crystal is used as the clock source, this pin must be set to 1.
The START pin must be tied to a logic 1 through a pull-up resistor, when
it is not used.
Use tcl script instead of static xmls for the interface.
Easier to maintain and are not gitignored.
Rename spi_master to spi_engine because every interface should be
prefixed by the IP name; in this case, spi_engine.
Also, remove interface/*.sv files on make clean and git ignore them.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
The introduction of sysid IPs on some Stratix 10 projects introduced a
problem where they would fail to build, due to mem_init_sys_file_path
not being defined. This is fixed now.
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Drop shell for loops in favor of makefile pattern rules,
so make can run targets in parallel using -j.
This doesn't affect Vivado's own settings.
As a benchmark, 12th Gen Intel(R) Core(TM) i9-12900H 5GHz(max):
$ make -C projects/adrv9009/zcu102/ clean-all
$ time make -C projects/adrv9009/zcu102/ -j$CORES lib
CORES=1:
real 9m27.223s
user 9m2.556s
sys 0m32.358s
CORES=8:
real 1m54.639s
user 16m26.512s
sys 1m2.317s
i.e. about 5 times faster to build IP core dependencies.
Signed-off-by: Liam Beguin <liambeguin@gmail.com>
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
axi_dac_interpolate - Remove last sample hold control
axi_ad9963 - Remove last sample hold control and set as default the
last sample hold functionality plus code optimization changes.
This commit makes the following changes:
Add SPI Engine for serial mode
Add SER_PAR_N build parameter, set default 1 for serial
Fix irq consistency in ad7616_bd.tcl
Fix regmap and offload names
Fix system_top.v GPIOs
* Projects: Add missing sysid IP
* Added make parameters for the sysid ip for the projects: ad9209_fmca_ebz/vck190, ad9213_dual_ebz/s10soc and adrv9009/s10soc
Signed-off-by: Pop Ioan Daniel <pop.ioan-daniel@analog.com>
Commit 5db7574 switched ad_cpu_interconnect from SmartConnect to
AXI Interconnect for Zynq-7000 family SoC. This commit does the
same for ad_mem_hpx_interconnect.
Signed-off-by: Alexander Vickberg <wickbergster@gmail.com>
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
I changed the comments from system_constr.xdc file.
Added pulsar_adc_pmdz_pmod.txt.
Tests were done on the eval-ad7689-ebz and eval-ad7984-pmdz boards.
Signed-off-by: Ioan-daniel Pop <Pop.Ioan-daniel@analog.com>
* Update cn0363 spi engine
I replaced the SPI Engine connections in the cn0363_bd.tcl with the
spi_engine_create procedure found in the spi_engine.tcl script. Through
these changes, a more generic instantiation for the spi_engine can be
achieved. I updated the system_constr.xdc file and
created the cn0363_pmod.txt file.
Signed-off-by: Ioan-daniel Pop <Pop.Ioan-daniel@analog.com>
* Update ad469x spi engine
I replaced the SPI Engine connections in the ad469x_bd.tcl with the
spi_engine_create procedure found in the spi_engine.tcl script. Through
these changes, a more generic instantiation for the spi_engine can be
achieved. I also created the ad469x_fmc.txt file for generating the
system_constr.xdc file.
Signed-off-by: Ioan-daniel Pop <Pop.Ioan-daniel@analog.com>
* Update SPI Engine AD738x
I replaced the SPI Engine connections in the ad738x_bd.tcl with the
spi_engine_create procedure found in the spi_engine.tcl script. Through
these changes, a more generic instantiation for the spi_engine can be
achieved. I changed the ad738x_bd.tcl where it was added spi_engine_create
procedure, system_bd.tcl and system_top.v files.
I have update system_constr.xdc file and added ad738x_fmc.txt file.
Signed-off-by: Ioan-daniel Pop <Pop.Ioan-daniel@analog.com>
In this project it was created the ad5766_fmc.txt file for generating the system_constr.xdc file.
Also it was updated the system_constr.xdc and Readme.md files.
Signed-off-by: Ioan-daniel Pop <Pop.Ioan-daniel@analog.com>
I replaced the SPI Engine connections in the adaq7980_bd.tcl with the
spi_engine_create procedure found in the spi_engine.tcl script. Through
these changes, a more generic instantiation for the spi_engine can be
achieved. I configured the parameters for axi_pwm_gen and axi_clkgen according
to the results in the SPI_Engine_Timing_Computations Excel where I created a file
for adaq7980.
I created the adaq7980_fmc.txt file for generating the system_constr.xdc file.
I modified the system_bd.tcl, system_top.v, system_constr.xdc and Readme.md files.
Also I regenerated the Makefile.
This commit adds support for ADALM-PHASER, allowing the user to choose between the default PlutoSDR mode and Phaser mode
through a software controlled GPIO pin: phaser_enable.
The Generic TDD Engine was integrated to output a logic signal on the L10P pin, which connects to the input of the ADF4159,
when receiving an external synchronization signal on the L12N pin from the Raspberry Pi. Two additional TDD channels are used
to synchronize the TX/RX DMA transfer start:
- TDD CH1 is connected to the RX DMA, triggering the synchronization flag;
- TDD CH2 is connected to the TX unpacker's reset, backpressuring the TX DMA until deasserted.
Signed-off-by: Ionut Podgoreanu <ionut.podgoreanu@analog.com>
Reference design for AD4858 20-bit, low noise 8-channel, SAR ADC with
buffered differential, wide common range picoamp inputs.
The design supports:
- CMOS and LVDS interfaces(at build time)
- Runtime sampling changes
- Store captured samples in RAM, through DMA (available via software support)
Documentation at: https://wiki.analog.com/resources/eval/user-guides/ad4858_fmcz/ad4858_fmcz_hdl
The project controls the AD3552R digital-to-analog converter and transmits data written in the DDR memory to the QSPI interface of the DAC.
The reference clock is generated by an axi_clkgen IP and is configured to output a 133MHz signal.
If both channels are enabled and data streaming is DDR the sample rate is 16.65MSPS.
If just one channel is enabled and data streaming is DDR the sample rate is 33.3MSPS.
The VADJ voltage should be set to 1.8V.
Signed-off-by: PopPaul2021 <Paul.Pop@analog.com>
Change necessary to build intel projects with different system_top verilog files.
This was patterned to ae09b8a1bb/projects/scripts/project-xilinx.mk (L70)
Signed-off-by: Jem Geronimo <Johnerasmusmari.Geronimo@analog.com>
PIoandan
Jorge Marques
ladace
Alin-Tudor Sferle
StancaPop
LBFFilho
AndrDragomir
Jorge Marques
AndreiGrozav
Iulia Moldovan
Liam Beguin
cristianmihaipopa
Ionut Podgoreanu
kylex
Bogdan Luncan
Ioan-daniel Pop
laurentiu_popa
Vilmos-Csaba Jozsa
Liviu.Iacob
PopPaul2021
Jem Geronimo
Jem Geronimo