Commit Graph

2 Commits (606551b4785c676a3e78dab247641e569cba78f2)

Author SHA1 Message Date
Iulia Moldovan 68461110aa Replace link in license header from master to main
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2024-01-16 16:48:45 +02:00
PopPaul2021 c29c092bdc projects/ad3552r_evb: Added project for AD3552R-EVB on ZedBoard.
The project controls the AD3552R digital-to-analog converter and transmits data written in the DDR memory to the QSPI interface of the DAC.
The reference clock is generated by an axi_clkgen IP and is configured to output a 133MHz signal.
If both channels are enabled and data streaming is DDR the sample rate is 16.65MSPS.
If just one channel is enabled and data streaming is DDR the sample rate is 33.3MSPS.
The VADJ voltage should be set to 1.8V.

Signed-off-by: PopPaul2021 <Paul.Pop@analog.com>
2023-10-02 11:07:08 +03:00