Rejeesh Kutty
|
6100a697e8
|
daq3/a10gx- alt 16.1 updates
|
2017-06-07 10:23:20 -04:00 |
|
Rejeesh Kutty
|
40bfd0380e
|
adrv9371x/a10gx- alt 16.1 updates
|
2017-06-07 09:19:14 -04:00 |
Istvan Csomortani
|
83747ddb33
|
ad77681evb: Fix IO constraints
|
2017-06-07 14:28:39 +03:00 |
|
Istvan Csomortani
|
7554887982
|
avl_dacfifo: Fix timing violation
+ Transfer avl_last_beats into dac clock domain
+ Update constraint file
|
2017-06-07 11:02:44 +01:00 |
Adrian Costina
|
b7ca17f02b
|
scripts: Change adi_project_create to adi_project_xilinx for creating xilinx projects
|
2017-06-07 12:06:50 +03:00 |
|
Rejeesh Kutty
|
d1bab7ddb9
|
hdlmake.pl- updates
|
2017-06-06 16:10:05 -04:00 |
|
Rejeesh Kutty
|
3f92381bd0
|
daq2/a10gx- project/constraint updates
|
2017-06-06 16:09:15 -04:00 |
|
Rejeesh Kutty
|
dd48929327
|
hdlmake.pl - updates
|
2017-06-06 12:25:35 -04:00 |
|
Rejeesh Kutty
|
5176e427a1
|
common/a10soc- add project create tcl procedure
|
2017-06-06 12:24:13 -04:00 |
|
Rejeesh Kutty
|
f278b6e6c9
|
adrv9371x/a10soc- constraints/project updates
|
2017-06-06 12:23:26 -04:00 |
|
Rejeesh Kutty
|
e34057c2b2
|
adrv9371x/a10gx- constraints/project updates
|
2017-06-06 12:22:31 -04:00 |
|
Rejeesh Kutty
|
e9c49f667f
|
altera- 16.1.2 & a10soc
|
2017-06-06 12:20:44 -04:00 |
|
Rejeesh Kutty
|
41d305b6b6
|
up_clock_mon- name changes
|
2017-06-06 11:36:18 -04:00 |
AndreiGrozav
|
4cc5052b3a
|
util_fir_int: Fix valid assignment
|
2017-06-06 17:53:41 +03:00 |
|
Adrian Costina
|
578ccaaa44
|
adrv9371x:a10gx, update create project command and Makefile
|
2017-06-06 17:30:12 +03:00 |
|
Adrian Costina
|
54a53c015a
|
scripts: changed adi_project_create command to adi_project_altera
|
2017-06-06 17:29:12 +03:00 |
|
Adrian Costina
|
0d99aa02e1
|
m2k: Updated project to work with the fifo_depth related changes
|
2017-06-06 15:37:23 +03:00 |
|
Adrian Costina
|
ac55e850a9
|
axi_logic_analyzer: Added trigger delay register, renamed fifo depth register
|
2017-06-06 15:37:00 +03:00 |
|
Adrian Costina
|
3148c85f73
|
axi_adc_trigger: Added trigger delay register, renamed fifo depth register
|
2017-06-06 15:35:59 +03:00 |
|
Istvan Csomortani
|
491602d88b
|
make: Update make files
|
2017-06-06 12:00:40 +03:00 |
|
Rejeesh Kutty
|
6df97a61ae
|
adrv9364z7020- fix enable/en_agc mixup
|
2017-06-05 16:06:27 -04:00 |
|
Rejeesh Kutty
|
eadbf9ae30
|
altera- remove default assignments from procedure
|
2017-06-05 15:25:38 -04:00 |
|
Rejeesh Kutty
|
0bd22e78d9
|
altera- adi-project-create version
|
2017-06-05 15:24:35 -04:00 |
|
Rejeesh Kutty
|
1b1c7ffa61
|
adi_project- altera version
|
2017-06-05 15:13:21 -04:00 |
|
Rejeesh Kutty
|
95c446a41d
|
adi_ip- initialize xdc list when ip is created
|
2017-06-01 15:49:18 -04:00 |
|
Rejeesh Kutty
|
6a437472f2
|
jesd204-sub-ip- no top files
|
2017-06-01 15:48:48 -04:00 |
|
Istvan Csomortani
|
50cdb6db67
|
Merge branch 'jesd204' into dev
|
2017-05-31 20:44:32 +03:00 |
|
Istvan Csomortani
|
cb4e8f66ef
|
axi_ad9963: Delete unused source from *_ip.tcl
|
2017-05-31 18:27:47 +03:00 |
|
Istvan Csomortani
|
84b2ad51e2
|
license: Add some clarification to the header license
|
2017-05-31 18:18:56 +03:00 |
|
Istvan Csomortani
|
b6d5dbf1fc
|
license: GPL must be GPL v2
|
2017-05-31 18:18:45 +03:00 |
|
Adrian Costina
|
3a4a91b6f1
|
util_extract: Estetic changes
|
2017-05-31 11:27:32 +03:00 |
|
Rejeesh Kutty
|
2d56141bbd
|
altera- 2017-r1 16.1.2
|
2017-05-30 12:21:27 -04:00 |
|
Adrian Costina
|
7aa1673238
|
util_extract: Update parameter names
|
2017-05-29 16:04:56 +03:00 |
|
Istvan Csomortani
|
9bb50f9e74
|
license: Add few cosmetic changes to LICENSE
|
2017-05-29 12:09:43 +03:00 |
|
Istvan Csomortani
|
cc5d758947
|
license: Update top level LICENSE file
This update reflects all the new and existed licensing terms.
|
2017-05-29 09:58:27 +03:00 |
|
Istvan Csomortani
|
9cb84456ee
|
license: Add top level license files
|
2017-05-29 09:57:39 +03:00 |
|
Istvan Csomortani
|
85ebd3ca01
|
license: Update license terms in hdl source files
Fix a few gramatical error, fix the path of the top level license
files.
|
2017-05-29 09:55:41 +03:00 |
|
Rejeesh Kutty
|
aaae350b3d
|
alt_serdes- 16.1 updates
|
2017-05-26 11:00:07 -04:00 |
|
Rejeesh Kutty
|
25e42c49d6
|
library: move alt cores to common
|
2017-05-26 10:51:25 -04:00 |
|
Rejeesh Kutty
|
ff037c0286
|
altera 16.1 ip changes
|
2017-05-26 10:48:00 -04:00 |
|
Rejeesh Kutty
|
097924b95d
|
altera 16.1 ip changes
|
2017-05-26 10:46:28 -04:00 |
|
Istvan Csomortani
|
669e0a01d0
|
fmcomms2/a10gx: Remove project
|
2017-05-26 17:05:55 +03:00 |
|
Istvan Csomortani
|
3c47d00a96
|
daq1/a10gx: Remove project
|
2017-05-26 17:05:28 +03:00 |
|
Istvan Csomortani
|
414943db4b
|
m2k: Fix Make files
|
2017-05-26 09:54:08 +03:00 |
|
Istvan Csomortani
|
c4fa41e4e5
|
adrv9364z7020: Update README
|
2017-05-25 17:47:58 +03:00 |
|
Istvan Csomortani
|
3af00dc520
|
adrv9361z7035: Update README
|
2017-05-25 17:47:19 +03:00 |
|
Istvan Csomortani
|
9ecfcce4ec
|
adrv9364z7020: Rename pzsdr1 to adrv9364z7020
|
2017-05-25 17:20:23 +03:00 |
|
Istvan Csomortani
|
26822af7e1
|
adrv9361z7035: Rename pzsdr2 to adrv9361z7035
|
2017-05-25 17:17:54 +03:00 |
|
Istvan Csomortani
|
4c998d1e18
|
make: Update make files
|
2017-05-25 15:12:17 +03:00 |
|
Istvan Csomortani
|
10898d6618
|
constraints: Split the regmap CDC constraint into separate file
|
2017-05-25 15:12:16 +03:00 |