Commit Graph

7 Commits (610cc3affa4f603f69040f1d2595504a2502927a)

Author SHA1 Message Date
Rejeesh Kutty fb4a583613 projects/system_bd- adc/dac fifo board designs 2017-02-27 16:06:39 -05:00
Rejeesh Kutty edd5e9570f file renamed; sed output; fingers crossed 2017-02-22 15:56:37 -05:00
Rejeesh Kutty ce1fed1ce6 dmafifo- adc/dac split 2016-08-16 12:54:39 -04:00
Istvan Csomortani 15618c9edf daq2 : Integrate the DACFIFO into the supported projects.
+ All pack/unpack logic is made by the cpack and upack modules.
+ The DAC FIFO is integrated between the TX DMA and cpack.
+ All the top files are updated, all the projects compiled successfully.
2015-05-11 12:20:50 +03:00
Rejeesh Kutty 6a85724793 daq2/vc707: 2014.4 updates 2015-03-26 14:02:31 -04:00
Rejeesh Kutty e111e1336e conflicts- 2015-02-06 22:14:21 -05:00
Istvan Csomortani e1d8dd10a9 daq2: Initial check in of the VC707 based project
NOTE: Can not communicate with the clock chip, rx/tx PLL not locking.
2015-01-28 16:24:06 +02:00