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23 Commits (610cc3affa4f603f69040f1d2595504a2502927a)

Author SHA1 Message Date
Istvan Csomortani 1c23cf4621 all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
AndreiGrozav d08d1d5a1b adrv9371x ,daq3, fmcomms7, fmcomms11: add dac_fifo missing reset connection 2017-03-10 14:20:42 +02:00
Rejeesh Kutty 6b1a8852a9 dacfifo- bypass port name change 2017-02-27 16:06:39 -05:00
Rejeesh Kutty daa3df4b96 projects/- xcvr updates 2016-11-22 16:23:05 -05:00
Adrian Costina 1d1fe26624 fmcomms7: ZC706, Update project to new GT framework 2016-10-14 17:32:23 +03:00
AndreiGrozav 1eccf5af07 fmcomms7: Update common design to Vivado 2016.2 2016-08-30 16:46:15 +03:00
AndreiGrozav abc03fff2c fmcomms7: Updated design to 2015.4 2016-03-17 09:11:41 +02:00
Adrian Costina 40fb68dfd5 ad9265, ad9434, ad9467, daq1, daq2, daq3, fmcadc2, fmcadc4, fmcadc5, fmcjesdadc1, fmcomms6, fmcomms7, usdrx1: updated common spi module so that spi streaming is possible 2016-03-02 13:39:37 +02:00
Istvan Csomortani f5b5bbfbca fmcomms7: Update to the new JESD framework 
Update project to the new framework for JESD interface and add a DAC FIFO to the transmit path.
 2015-09-25 19:11:12 +03:00
Istvan Csomortani fbd51c2734 fmcomms7: Update to 2015.2 
Update IP core version of jesd204.
 2015-09-25 19:11:10 +03:00
Lars-Peter Clausen 9210e1d58a fmcomms7: Drop explicit axi_dmac clock synchronicity configuration 
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2015-09-18 15:28:11 +02:00
Istvan Csomortani d52308f074 axi_dmac: Change parameter name 2D_TRANSFER 
Parameter name can't start with numbers, 2D_TRANSFER was changed to DMA_2D_TRANSFER
 2015-08-20 10:14:22 +03:00
Istvan Csomortani 57cfb7cfb1 hdl/library: Update the IP parameters 
The following IP parameters were renamed:

PCORE_ID --> ID
PCORE_DEVTYPE --> DEVICE_TYPE
PCORE_IODELAY_GROUP --> IO_DELAY_GROUP
CH_DW --> CHANNEL_DATA_WIDTH
CH_CNT --> NUM_OF_CHANNELS
PCORE_BUFTYPE --> DEVICE_TYPE
PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE
CHID --> CHANNEL_ID
PCORE_DEVICE_TYPE --> DEVICE_TYPE
PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N
PCORE_SERDES_DDR_N --> SERDES_DDR_N
PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE
DP_DISABLE --> DATAPATH_DISABLE
PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE
C_BIG_ENDIAN --> BIG_ENDIAN
C_M_DATA_WIDTH --> MASTER_DATA_WIDTH
C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH
NUM_CHANNELS --> NUM_OF_CHANNELS
CHANNELS --> NUM_OF_CHANNELS
PCORE_4L_2L_N -->QUAD_OR_DUAL_N
C_ADDRESS_WIDTH --> ADDRESS_WIDTH
C_DATA_WIDTH --> DATA_WIDTH
C_CLKS_ASYNC --> CLKS_ASYNC
PCORE_QUAD_DUAL_N --> QUAD_DUAL_N
NUM_CS --> NUM_OF_CS
PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID
PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID
PCORE_CLK0_DIV --> CLK0_DIV
PCORE_CLK1_DIV --> CLK1_DIV
PCORE_CLKIN_PERIOD --> CLKIN_PERIOD
PCORE_VCO_DIV --> VCO_DIV
PCORE_Cr_Cb_N --> CR_CB_N
PCORE_VCO_MUL --> VCO_MUL
PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC
PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH
PCORE_ADDR_WIDTH --> ADDRESS_WIDTH
DADATA_WIDTH --> DATA_WIDTH
NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS
DEBOUNCER_LEN --> DEBOUNCER_LENGTH
ADDR_WIDTH --> ADDRESS_WIDTH
C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED
Cr_Cb_N --> CR_CB_N
ADDATA_WIDTH --> ADC_DATA_WIDTH
BUFTYPE --> DEVICE_TYPE
NUM_BITS --> NUM_OF_BITS
WIDTH_A --> A_DATA_WIDTH
WIDTH_B --> B_DATA_WIDTH
CH_OCNT --> NUM_OF_CHANNELS_O
M_CNT --> NUM_OF_CHANNELS_M
P_CNT --> NUM_OF_CHANNELS_P
CH_ICNT --> NUM_OF_CHANNELS_I
CH_MCNT --> NUM_OF_CHANNELS_M
4L_2L_N --> QUAD_OR_DUAL_N
SPI_CLK_ASYNC --> ASYNC_SPI_CLK
MMCM_BUFIO_N --> MMCM_OR_BUFIO_N
SERDES_DDR_N --> SERDES_OR_DDR_N
CLK_ASYNC --> ASYNC_CLK
CLKS_ASYNC --> ASYNC_CLK
SERDES --> SERDES_OR_DDR_N
GTH_GTX_N --> GTH_OR_GTX_N
IF_TYPE --> DDR_OR_SDR_N
PARALLEL_WIDTH --> DATA_WIDTH
ADD_SUB --> ADD_OR_SUB_N
A_WIDTH --> A_DATA_WIDTH
CONST_VALUE --> B_DATA_VALUE
IO_BASEADDR --> BASE_ADDRESS
IO_WIDTH --> DATA_WIDTH
QUAD_DUAL_N --> QUAD_OR_DUAL_N
AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT
ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH
ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH
MODE_OF_ENABLE --> CONTROL_TYPE
CONTROL_TYPE --> LEVEL_OR_PULSE_N
IQSEL --> Q_OR_I_N
MMCM --> MMCM_OR_BUFR_N
 2015-08-19 14:11:47 +03:00
Lars-Peter Clausen 6862655b0d Add .gitattributes file 
Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2015-06-26 11:07:10 +02:00
Rejeesh Kutty 71b5004b25 projects- drp moved to up-clock domain 2015-06-01 14:57:59 -04:00
Rejeesh Kutty 26a1f48724 fmcomms7: dac lane mux 2015-04-03 13:42:27 -04:00
Rejeesh Kutty 8cb96533d3 fmcomms7: 2014.4 updates 2015-03-17 14:01:46 -04:00
Rejeesh Kutty f01d1aae2d fmcomms7: compilation fixes on plddr3 2014-12-02 10:38:44 -05:00
Rejeesh Kutty b96a8d01c3 fmcomms7: asymmetric no of lanes 2014-11-11 08:54:25 -05:00
Rejeesh Kutty 87000d7a23 fmcomms7: board updates 2014-11-10 13:26:26 -05:00
Rejeesh Kutty cbcdf4a2aa fmcomms7: initial updates 2014-11-10 13:26:20 -05:00
Rejeesh Kutty 1edef2b8ff fmcomms7: initial updates 2014-11-10 13:26:19 -05:00
Rejeesh Kutty 12896c7624 fmcomms7: daq2 copy 2014-11-10 13:26:18 -05:00