89f5d2394e
altera- clock variations
2016-04-29 10:17:35 -04:00
243d3e6e41
ad9361- a10soc sdc files
2016-04-29 10:17:35 -04:00
aa2aa902bf
ad9361- a10soc updates
2016-04-29 10:17:35 -04:00
f411d29e30
ad9361- a10soc changes
2016-04-29 10:17:35 -04:00
3563c2212c
common/altera- removed dcfilt/mul
2016-04-29 10:17:35 -04:00
0260280db1
common/altera- data path
2016-04-29 10:17:35 -04:00
ed62101308
common/altera: primitives
2016-04-29 10:17:35 -04:00
779d014750
ad9361-common alt/xil interface
2016-04-29 10:17:35 -04:00
e9b199959a
library/adcfifo- constraints update
2016-04-20 15:57:25 -04:00
679d471d75
Merge branch 'hdl_2016_r1' into dev
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hdl_2016_r1 contains IP core upgrades to Vivado 2015.4.2 and hdmi_tx improvements.
2016-04-19 18:05:50 +03:00
d7d8b2cf1c
axi_usb_fx3: Integrated actual GPIF II interface, with 2 address lines
2016-04-19 14:38:26 +03:00
e855ef38f4
axi_dacfifo: Initial commit
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AXI DAC fifo, which use the PL side DDR memory. The minimum data granularity is 1kbyte.
2016-04-19 11:28:33 +03:00
42cd05ab19
ad_mem_asym: Add support for more ratios.
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Supported ratios: 1:1/1:2/1:4/1:8/2:1/4:1/8:1
2016-04-19 11:18:30 +03:00
6fe41ebb08
axi_hdmi_tx: Upgrade hdmi clipping process
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-added two registers that control the clipping ranges (0x01a and 0x01b)
-extend clipping process for all output data formats
2016-04-12 22:01:07 +03:00
69d721526a
util_dacfifo: Add constraints file
2016-04-12 13:21:50 +03:00
255b0ebd40
util_dacfifo: Add dac_xfer_out control
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The dac_xfer_out control signal is asserted while the DAC reads back data. Should be connected to upack/dma_xfer_in.
2016-03-29 16:50:00 +03:00
b31cdac6bd
util_gmii_to_rgmii: Updated to 2015.4
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The Xilinx interface changed its name from gmii_rtl_1 to gmii_rt_1
2016-03-23 10:14:18 +02:00
46eddd04be
library: port updates on mmcm
2016-03-22 12:50:59 -04:00
de4da6726b
axi_clkgen: port updates on mmcm
2016-03-22 12:50:59 -04:00
74408881c6
axi_ad9122: optional clock out control
2016-03-22 12:50:59 -04:00
65b2e51958
common/mmcm: add another clock
2016-03-22 12:50:59 -04:00
769fecbe00
axi_i2s_adi: Fixed clock association
2016-03-21 20:18:45 +02:00
373481360b
util_dacfifo: Add a bypass option to the FIFO
2016-03-21 14:14:43 +02:00
6d277733d5
axi_spdif_rx: Fixed the clock association
2016-03-18 13:58:13 +02:00
28990e362a
axi_spdif_tx: Fixed the clock association
2016-03-18 13:31:06 +02:00
896c734792
Revert "foobar"
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This reverts commit a3cb8cac45
2016-03-18 13:23:02 +02:00
a3cb8cac45
foobar
2016-03-18 11:51:13 +02:00
9b2a106aa0
axi_jesd_gt: changed clock and reset naming to be consistent with the other projects
2016-03-15 11:20:31 +02:00
06b7916303
axi_spdif_tx: changed adi_ip_properties_lite to adi_ip_properties, so that the axi interface can be inferred
2016-03-15 10:18:25 +02:00
ef05642e26
axi_spdif_rx: changed adi_ip_properties_lite to adi_ip_properties, so that the axi interface can be inferred
2016-03-15 10:14:05 +02:00
b3ed38107c
axi_i2s_adi: changed adi_ip_properties lite to adi_ip_properties, so that the axi interface can be inferred
2016-03-15 10:12:45 +02:00
8ecf5edaf8
ad9122- pat modes
2016-03-14 11:14:29 -04:00
31cc91d1b9
adi_ip: Updated to 2014.4.2
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- automatically infer clocks, resets, axim_mm and axis interfaces
2016-03-14 15:14:18 +02:00
33b265a742
Makefile: Update Makefiles
2016-03-14 09:31:17 +02:00
287770a201
axi_dmac: Fix tlast generation on AXI stream master
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For the AXI stream interface we want to generate TLAST only at the end of
the transfer, rather than at the end of each burst.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-03-08 10:53:59 +01:00
2524f19ae0
Updated interfaces Makefile and Makefiles for the libraries that depend on it
2016-03-07 12:31:41 +02:00
583ef82fd0
ad9361- cmos mode
2016-03-04 10:39:48 -05:00
7a320a3d34
ad_lvds* - updates
2016-03-04 10:39:48 -05:00
7d2939be92
ad9361- cmos mode initial commit
2016-03-04 10:39:48 -05:00
377461e0d4
Merge branch 'hdl_2015_r2' into dev
2016-02-19 14:15:27 +02:00
a8e9d72273
adc/dac - prefix parameters
2016-02-17 14:16:04 -05:00
e1c5d6a8f7
axi_ad9684: Fix constraint file
2016-02-12 14:38:59 +02:00
a747fad540
axi_ad9361: tx_valid must be controlled by the TDD controller
2016-02-12 14:33:34 +02:00
e381d5170c
util_tdd_sync: Update the synchronization interface
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Simplify the synchronization interface, there is one signal line between the synchronization module and transceiver core.
2016-02-12 14:27:37 +02:00
0d67af370f
util_upack: Fixed problem when dac valid isn't continuous from the DAC
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In cases when the dac_valid_ from the DAC is not continuous, in some situations
there were two dac_valid pulses sent to the DMA.
2016-02-04 13:03:46 +02:00
4cc69c0cac
axi_ad9684: Add Makefile
2016-01-19 18:32:11 +02:00
c865dbf353
axi_ad9680: Fix channel instantiation
2016-01-19 12:49:45 +02:00
df3eefdca1
axi_ad9434: Update constraint file
2016-01-19 12:43:05 +02:00
d1e638349b
ad_serdes_clk : The reference clock selection line should by tied to 1
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Just the CLKIN1 is used in the MMCM.
2016-01-19 11:18:00 +02:00
c6cfd1a2b6
axi_ad9684: Initial check in
2016-01-19 11:13:45 +02:00
Rejeesh Kutty
AndreiGrozav
Adrian Costina
Istvan Csomortani
Lars-Peter Clausen
István Csomortáni