2912372d6e
ad9625_fmc: Add support for AD-JESDCLOCK1-EBZ
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Connect the SPARE_CLOCK_DUT pin to GPIO, this will be used to reset the AD9527.
The SPI interface for the clock chip is already integrated into the design.
2014-11-18 14:11:51 +02:00
2eb80715e3
ad9625_fmc: dma fifo changes
2014-11-13 14:13:00 -05:00
897f5e219d
ad9625_zc706: Update GT configuration
2014-11-11 19:25:30 +02:00
d55ddc4da5
ad9625_vc707: Delete SEG_axi_bram_ctl_mem memory segment
2014-11-06 15:01:12 +02:00
8ed9d10502
ad9625_fmc: disable sync
2014-10-31 13:05:18 -04:00
cc265b6b9c
daq2/daq3/ad9625_fmc: Connect ADC DMA xfer_req signal
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For proper operation the xfer_req signal needs to be connected from the ADC DMA to the DDR FIFO.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-29 18:15:54 +01:00
4788d09620
vc707: interrupt updates
2014-10-28 15:42:55 -04:00
c9691fac64
ad9625_fmc: merge zc706 and vc707
2014-10-28 10:12:19 -04:00
627da6161b
ad9625_fmc: remove dma clock for now - zynq/non-zynq merge
2014-10-28 10:12:18 -04:00
17675863e0
all_projects: Fix the interrupt connections to preserve IRQ layout
2014-10-22 11:48:08 +03:00
7f8270d74b
ad9625_fmc: generic dma fifo for zynq and non-zynq boards
2014-10-17 14:38:16 -04:00
f0927afd0b
ad9625_fmc: add dma fifo for non-zynq
2014-10-01 14:51:14 -04:00
a3dbd5ac00
projects/common/vc707/vc707_system_bd: AD9625_FMC update to 2014.2
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Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
2014-09-16 14:59:36 +02:00
f2bf5ced04
ad9625: register map updates
2014-07-03 14:30:03 -04:00
2d27f88588
ad9625_fmc, ad9625x2_fmc: initial checkin
2014-06-09 16:40:48 -04:00
Istvan Csomortani
Rejeesh Kutty
Lars-Peter Clausen
Michael Hennerich