Adrian Costina
b54dab33e0
Make: Update makefiles
2017-11-20 14:27:39 +02:00
Adrian Costina
37323e3444
adrv9371x: A10GX, added extra pipelining in the interconnect in order to improve timing
2017-10-20 13:46:22 +01:00
Istvan Csomortani
be4e02aed9
adrv9371x/a10gx: Add external flash support
2017-10-06 08:43:58 +01:00
Istvan Csomortani
700ed156ab
[axi|avl]_dacfifo: Create a separate bypass module for altera/xilinx
2017-09-25 08:56:40 +01:00
Lars-Peter Clausen
e4988aa131
adrv9371x: altera: Convert to ADI JESD204
...
Convert the ADRV9371 project for Intel/Altera platforms to the ADI JESD204
framework.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-24 17:55:10 +02:00
Istvan Csomortani
6ebef5dde0
make: Update make files
2017-06-26 15:51:19 +01:00
Rejeesh Kutty
40bfd0380e
adrv9371x/a10gx- alt 16.1 updates
2017-06-07 09:19:14 -04:00
Rejeesh Kutty
e34057c2b2
adrv9371x/a10gx- constraints/project updates
2017-06-06 12:22:31 -04:00
Adrian Costina
578ccaaa44
adrv9371x:a10gx, update create project command and Makefile
2017-06-06 17:30:12 +03:00
Rejeesh Kutty
0bd22e78d9
altera- adi-project-create version
2017-06-05 15:24:35 -04:00
Istvan Csomortani
50cdb6db67
Merge branch 'jesd204' into dev
2017-05-31 20:44:32 +03:00
Istvan Csomortani
84b2ad51e2
license: Add some clarification to the header license
2017-05-31 18:18:56 +03:00
Istvan Csomortani
85ebd3ca01
license: Update license terms in hdl source files
...
Fix a few gramatical error, fix the path of the top level license
files.
2017-05-29 09:55:41 +03:00
Istvan Csomortani
4c998d1e18
make: Update make files
2017-05-25 15:12:17 +03:00
Lars-Peter Clausen
01aea161fa
Create CDC helper library
...
Move the CDC helper modules to a dedicated helper modules. This makes it
possible to reference them without having to use file paths that go outside
of the referencing project's directory.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-23 11:16:07 +02:00
Rejeesh Kutty
4f0accbbfa
adrv9371x fix dacfifo name
2017-05-18 12:54:14 -04:00
Istvan Csomortani
9055774795
all: Update license for all hdl source files
...
All the hdl (verilog and vhdl) source files were updated. If a file did not
have any license, it was added into it. Files, which were generated by
a tool (like Matlab) or were took over from other source (like opencores.org),
were unchanged.
New license looks as follows:
Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
Each core or library found in this collection may have its own licensing terms.
The user should keep this in in mind while exploring these cores.
Redistribution and use in source and binary forms,
with or without modification of this file, are permitted under the terms of either
(at the option of the user):
1. The GNU General Public License version 2 as published by the
Free Software Foundation, which can be found in the top level directory, or at:
https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
OR
2. An ADI specific BSD license as noted in the top level directory, or on-line at:
https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
2017-05-17 11:52:08 +03:00
Adrian Costina
942d69a30c
Makefiles: Change MMU enabling parameter for altera designs from MMU to NIOS2_MMU
2017-04-18 10:57:16 +03:00
Rejeesh Kutty
8eb1dd0a8b
adrv9371x/altera- xilinx/chip-select consistency
2017-03-29 12:59:09 -04:00
Rejeesh Kutty
8f1564a9c4
adrv9371x/a10gx- gpio matching
2017-03-27 13:51:45 -04:00
Rejeesh Kutty
8063ba2b66
make updates
2017-03-20 16:05:18 -04:00
Rejeesh Kutty
936c441763
adrv9371x- dacfifo bypass-gpio control
2017-03-06 10:35:09 -05:00
Rejeesh Kutty
ec89b1a45f
altera/adrv9371x- add dacfifo
2017-03-01 15:52:07 -05:00
AndreiGrozav
0cc5130c9a
adrv9371x: Set XCVR Tx/RX clk/data voltage levels at 1V
2017-03-01 11:32:17 +02:00
Rejeesh Kutty
4a783d523d
projects/altera* - default & common qsys commands
2016-12-20 16:27:44 -05:00
Adrian Costina
8ebc8fe4e2
updated makefiles
2016-12-09 23:06:41 +02:00
Rejeesh Kutty
2d7fb03b93
adrv9371x/a10gx- fix os xcvr parameters
2016-12-06 12:31:40 -05:00
Adrian Costina
ce3b6a2d3f
adrv9371x: Updated constraints for altera projects
2016-11-04 18:20:46 +02:00
Rejeesh Kutty
671a547c2b
hdlmake- updates
2016-11-01 12:41:25 -04:00
Rejeesh Kutty
50552ce7d6
adrv9371x- altera updates
2016-10-27 09:25:00 -04:00
Rejeesh Kutty
cb97bc500a
hdlmake updates
2016-10-17 16:29:57 -04:00
Adrian Costina
500d8bfb90
adrv9371x: A10GX, fix makefile and system_qsys.tcl script
2016-09-21 18:11:35 +03:00
Istvan Csomortani
16ee1336c3
Makefile: Update make files
2016-09-15 11:41:06 +03:00
Adrian Costina
3c6cfdc7b5
adrv9371x: A10GX, switched TX lanes
2016-08-24 18:06:14 +03:00
Rejeesh Kutty
f697490de6
hdlmake- updates
2016-08-19 15:59:41 -04:00
Adrian Costina
41203d07e9
adrv9371x: A10GX, update SPI connection
2016-08-18 17:42:27 +03:00
Adrian Costina
eb55f600fb
adrv9371x: Initial commit
...
-need to fix dc filter module for AD9371 / altera
2016-08-16 15:50:46 +03:00