Commit Graph

8 Commits (634601776327a0f50db0412657238b5a78e9b554)

Author SHA1 Message Date
Istvan Csomortani fbafaa8507 MicroBlaze base system: Fix a few net names
Every interconnect interface net name follows the convention:
	<interconnect name>_<interface name>
	No changes in logic or any connection!
2014-04-01 10:40:35 +03:00
Istvan Csomortani 0f10623be4 AC701/VC707: Define common variables
Define variables sys_zynq, sys_mem_size, sys_addr_cntrl_space.
2014-03-25 14:24:51 +02:00
Istvan Csomortani b94acf78aa AC701 bases sys: Add an auxiliary cpu interconnect
- Add an auxiliary cpu interconnect, the KC705 base system was
	  used as reference
	- Base system is tested and working
2014-03-24 13:01:52 +02:00
Istvan Csomortani 8a08031dce AC701: Modify interrupt concatenation
- Interrupt concatenation is the same as in case of KC705
2014-03-24 10:20:56 +02:00
Istvan Csomortani 3a0d1282b7 Fix the remaining issues
- Swap the IO locations of ports vsync and hsync
	- Change the mem_interconnect optimization strategy to Maximize
	  Performance
2014-03-20 14:36:01 +02:00
Istvan Csomortani 7cdab9b5b0 Change the internal clock generator to Clock Wizard
- Using a Clock Wizard Module, in place of the DDR Controler's MMCM for internal clock
	  generation.
2014-03-18 17:24:45 +02:00
Rejeesh Kutty 5c3b65d01b adv7511: kc705/ac701 updates 2014-03-06 09:36:50 -05:00
Rejeesh Kutty 360f10395a initial checkin 2014-03-03 13:42:25 -05:00