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Author SHA1 Message Date
David Winter f2017050ed axi_ad9361: Fix typo in tdd interface 
As alluded to in the subject, this commit simply fixes what appears
to be a copy-paste bug.

Signed-off-by: David Winter <david.winter@analog.com>
 2021-06-14 16:50:47 +03:00
Laszlo Nagy bf77271fb3 axi_adxcvr: Increase version to 17.4.a 
Add support for:
  - 204C support for GTH
  - added second clock output for util_xcvr used in case for GTH
  - PROG_DIV support for GTH and GTY
 2021-06-10 09:53:43 +03:00
Laszlo Nagy 505142f7f8 xilinx/axi_adxcvr: Expose PLL status in status bit 2021-06-10 09:53:43 +03:00
Laszlo Nagy b4c8a559fc util_adxcvr: Hook up RXPROGDIVRESET 2021-06-10 09:53:43 +03:00
Laszlo Nagy 75b965e87f ad9081_fmca_ebz/zcu102: Enable 204C modes 2021-06-10 09:53:43 +03:00
Laszlo Nagy 6637436c2e scripts/adi_board.tcl: Use div2 out clock from xcvr in case of GTH and 204C 2021-06-10 09:53:43 +03:00
Laszlo Nagy d743406ecd util_adxcvr: Add 204C support for GTH3/4 
For GTH3/4  64b66b mode add a second clock that drives CLKUSR with a clock
that is 2x of the CLKUSR2 (lane rate/66),
   CLKUSR = 2 x CLKUSR2
   CLKUSR = lane rate / 33

This can be driven from the GT reference clock or second out clock div2.

This commit also:
- fix eyescan scale on GTY
- remove irrelevant parameters
 2021-06-10 09:53:43 +03:00
Laszlo Nagy c0775adac3 util_adxcvr/util_adxcvr_xch: Place 204C logic to a common place 2021-06-10 09:53:43 +03:00
Laszlo Nagy 27465ce9c0 ad9081_fmca_ebz/zcu102: Fix spaces 2021-06-10 09:53:43 +03:00
sergiu arpadi 7b7609d21a ad469x: Clean system_project.tcl 2021-06-03 15:41:58 +03:00
Alin-Tudor Sferle 54c65013aa
Fix registers mismatches in regmap_tb from jesd 204 rx/tx and dmac 
* dmac_tb: Fix regmap_tb registers mismatches

* jesd204: Fix jes204 rx and tx regmap_tb Octets per multiframe mismatch
 2021-05-31 16:47:12 +03:00
Laszlo Nagy aa180fb272 axi_adrv9001: Let gate signals have initial value, useful for simulation 2021-05-26 15:44:45 +03:00
Laszlo Nagy b85784ebe8 axi_adrv9001: rx: calculate ramp value based on received value 2021-05-26 15:44:45 +03:00
Laszlo Nagy 9a93b56882 axi_adrv9001:rx: Add reset to link layer 
Fix random valid signals after resets on the Rx interface.
 2021-05-26 15:44:45 +03:00
Laszlo Nagy 4c35af74d4 axi_adrv9001:rx:phy: do not generate valid while in reset 2021-05-26 15:44:45 +03:00
Laszlo Nagy 32dbde6945 axi_adrv9001: Allow running Rx2/Tx2 channels in R1 mode without Rx1/Tx1 
This commit removes the deadlock created while trying to use the Rx2/Tx2
channels without the Rx1/Tx1 channels enabled first.
 2021-05-26 15:44:45 +03:00
Laszlo Nagy 1502b940d3 common/up_dac_common: Expose r1_mode in up clock domain to prevent deadlock 
If R1 mode is first syncronized to the dac clock domain will prevent its
usage if the dac clock is missing. In such case the synchronization will not
propagate.
 2021-05-26 15:44:45 +03:00
Laszlo Nagy d9bc014c98 adrv9001/zcu102: Enable independent Tx from Rx in CMOS mode 2021-05-26 15:44:45 +03:00
Laszlo Nagy 08b0d19731 axi_adrv9001: Populate correct ratio of the SSI interface and user interface clocks 
Depending on FPGA technology the physical layer uses different
deserialization factors and corresponding clock division factors to
divide the source synchronous interface clock. This must be
exposed to software so it can act on it while setting the DDS rate.

Xilinx CMOS clock ratio - 4
Xilinx LVDS clock ratio - 4
Intel  CMOS clock ratio - 1
 2021-05-26 15:44:45 +03:00
Laszlo Nagy 568bef4a38 adrv9001/a10soc: Initial version 
This project supports CMOS mode only.
 2021-05-26 15:44:45 +03:00
Owen McAree 5d008c3eca Correct constraints file pin mapping 2021-05-25 16:27:58 +03:00
Laszlo Nagy 0ad691a603 ad9081_fmca_ebz/zcu102: Differentiate parameters based on lane rate 2021-05-14 15:39:40 +03:00
Laszlo Nagy 8183599b51 ad9081_fmca_ebz/zcu102: Fix typo 2021-05-14 15:39:40 +03:00
Laszlo Nagy cf7f45ffcc ad9081_fmca_ebz: Fix for F=8 2021-05-14 15:39:40 +03:00
Laszlo Nagy 9b50e2baa5 util_adxcvr/util_adxcvr_xch: Fix typo 2021-05-14 15:39:40 +03:00
Laszlo Nagy 7b2ba41bdd ad9081_fmca_ebz/vcu118: Adjust QPLL params and diff swing 
This commit fixes the 16.5Gbps lane rate case where the link drops
after few seconds an initial successful link up happens.
A few seconds delayed calibration process can workaround this but with
having the differential drivers swing increased this is no longer
required.
 2021-05-14 15:39:40 +03:00
Laszlo Nagy e1b73545e4 util_adxcvr: GTY TX phase and delay alignment circuit power down. 
Tied High when a) TX buffer bypass is not in use;
see UG578
 2021-05-14 15:39:40 +03:00
Laszlo Nagy ef69fe36db util_adxcvr: Add PPF1_CFG parameter 2021-05-14 15:39:40 +03:00
Laszlo Nagy eba3409d78 ad9082_fmca_ebz: Use 9081 system_bd, updated comments 2021-05-14 15:39:40 +03:00
Laszlo Nagy 0d9e38bdbe ad9081_fmca_ebz: Update path to common block design 
Use absolute paths so ad9082 wrapper project can include the
system_bd.tcl instead of duplicating code.
 2021-05-14 15:39:40 +03:00
Laszlo Nagy 680d28476c ad9081_fmca_ebz: Add LANE_RATE param to all projects 
The block design expects a lane rate to be set in the system project.
 2021-05-14 15:39:40 +03:00
Laszlo Nagy bd6ec360e2 ad9081_fmca_ebz/vcu118: Set XCVR params for 204C link 
Set XCVR parameter for 204C 24.75 Gbps with a  dynamic range of 10Gbps..24.75Gpbs

Organize XCVR params based on lane rate
 2021-05-14 15:39:40 +03:00
Laszlo Nagy 693c002668 ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd: Add 204C support for XCVR 
Remove Xilinx PHY and simplify project
 2021-05-14 15:39:40 +03:00
Laszlo Nagy d92f925b06 ad9081_fmca_ebz: Disable XBAR from DAC TPL 2021-05-14 15:39:40 +03:00
Laszlo Nagy 001e7a52b1 util_adxcvr: Add LANE_RATE parameter so it can be used for automatic constraint generation 
Add separate LANE_RATE for TX and RX
 2021-05-14 15:39:40 +03:00
Laszlo Nagy cb5e66ff9c xilinx/util_adxcvr: 204C link support for GTY4 
Set channel parameters based on link mode (1 - 204b or 2 - 204c).
 2021-05-14 15:39:40 +03:00
Laszlo Nagy 2d13b5b8cd xilinx/axi_adxcvr: Add 204C support, increase version to 17.3.a 2021-05-14 15:39:40 +03:00
Laszlo Nagy 77a5edaa83 scripts/adi_board.tcl: In 204C do not connect SYNC 
Take link mode parameter from util_adxcvr, check it against the axi_adxcvr.
 2021-05-14 15:39:40 +03:00
Laszlo Nagy 60612720cd jesd204/jesd204_common/sync_header_align: Initial version 
This module creates sync header alignment described in section 7.6.1 of
the JESD 204C specification.

The alignment relies on the bitslip capability of the connected
transceiver.
 2021-05-14 15:39:40 +03:00
Laszlo Nagy 0c0c6843e3 jesd204/axi_jesd204: Complete clock definitions in out of context mode 2021-05-14 15:39:40 +03:00
Laszlo Nagy e08ca2fc20 jesd204: Add out of context constraint file for link layer cores 
For the out of context flow it is important to have all clocks defined
at the interface, especially if the clock are used in the other constraints.
 2021-05-14 15:39:40 +03:00
AndreiGrozav b4c5031272 axi_pulse_gen: Fix typo introduced in c235e5e58 2021-05-10 13:26:30 +03:00
stefan.raus 37238916df Testbenches: Unify and optimize HDL testbenches 
Create a common 'run_tb.sh' script to be called by every testbench.
Unify file and testbenches names.
Fix util_pack/cpack_tb.
Add parameters '-batch' and '-gui' for modelsim and xsim simulators (default is gui)
Add ascript for that generates output in xml format (used by CI tools).
 2021-05-07 19:53:14 +03:00
AndreiGrozav c235e5e583 axi_pwm_gen: Initial commit 
axi_pwm_gen is based on util_pulse_gen, it introduces the option of
phase option between pulses(PWMs) and external synchronization.
Documentation available at
https://wiki.analog.com/resources/fpga/docs/axi_pwm_gen
 2021-05-07 19:09:32 +03:00
Laszlo Nagy 1db04a47b8 ad9083_evb: Update parameters to 10Gpbs lane rate 2021-04-19 13:21:34 +03:00
vladimirnesterov 8335e1bd9a sysid: Make sure gitbranch_string is always declared 
Parsing of not existed "gitbranch_string" fails the build process.
 2021-03-24 13:34:32 +02:00
Sergiu Arpadi 6a374ef457 ad469x/zed: Add multicycle path constraint 2021-03-22 13:05:05 +02:00
stefan.raus 9413afa41c jesd204_rx_constr.ttcl: Remove ASYNC_REG constraint from i_lmfc/cdc_sync_stage1_reg 
get_cell on i_lmfc/cdc_sync_stage1_reg doesn't return anything because design was updated.
This generates a CRITICAL WARNING and since the constraint it not necessary anymore, it can be deleted.
 2021-03-22 10:55:00 +02:00
Laszlo Nagy cdd6c92357 xilinx/axi_adxcvr: Increase version to 17.02.a to show PRBS capability 2021-03-22 10:17:10 +02:00
Laszlo Nagy 5f2681314f xilinx/axi_adxcvr/axi_adxcvr_up: Fix force error control bit 2021-03-22 10:17:10 +02:00