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2448 Commits (64c8fd7e5e9a90b9eb40e7a8ecb77d39f9661365)

Author SHA1 Message Date
AndreiGrozav 8403ff17ec adrv9371x/kcu105: Use ultrascale type primitives in axi_clkgen IP 2018-02-13 17:33:38 +02:00
AndreiGrozav 2302d3516d adrv9371x:kcu105: Update transceiver configuration 2018-02-13 17:33:38 +02:00
Adrian Costina 73ef0fb48c adrv9371x: kcu105: Fix transceiver and clock placement 2018-02-13 17:33:38 +02:00
Istvan Csomortani bf3ba4426c fmcomms11: Update the SPI IO definitions 2018-01-29 18:48:31 +02:00
Istvan Csomortani 55b4603e60 fmcomms11: Update the clock tree 
- one single reference clock for both rx and tx channels
  - delete the SYSREF inputs
  - update the IO location of the usr_clk
 2018-01-29 18:44:15 +02:00
Istvan Csomortani ff562e7165 fmcomms11: Delete trailing whitespaces 2018-01-29 17:46:54 +02:00
Michael Hennerich 2e59a70cdd adrv9371: Increase FCLK2 to 200MHz to support max sampling rates 
This fixes an issue seen when using 307.2 MSPS on the Observation RX.

Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
 2018-01-09 15:20:06 +01:00
Istvan Csomortani 3b4aaec926 daq2: Data underflow of DAC FIFO is monitored by the device core 2017-12-09 10:52:05 +00:00
Adrian Costina 386febaa7e fmcadc5: Allow JESD reset from the ADC core, useful for synchronization 2017-11-29 16:03:00 +02:00
Adrian Costina 3e565bc03c fmcadc5: Disable constraints for jesd sysref in order to remove critical warning 2017-11-24 14:48:38 +02:00
AndreiGrozav ec324652aa daq2_zcu102: Fix typo 2017-11-20 18:02:22 +02:00
AndreiGrozav a23c640180 Require Vivado 2017.2.1 for all zcu102 projects 2017-11-20 15:36:51 +00:00
AndreiGrozav f1e51a8b89 adrv9371x_zcu102: Fix rx_div_clk constraint placement 2017-11-20 15:36:51 +00:00
Adrian Costina 7759bfdf96 fmcadc5: Update make 2017-11-20 15:16:30 +02:00
Adrian Costina c07fefcbd7 fmcadc5: Update to the ADI JESD interface 2017-11-20 15:12:47 +02:00
Adrian Costina b54dab33e0 Make: Update makefiles 2017-11-20 14:27:39 +02:00
AndreiGrozav 76cec098d1 daq2, daq3: zcu102: Update constraints 
Differential pins ignored by the tool
 2017-11-15 10:47:01 +02:00
Lars-Peter Clausen 8fa50a0cb4 daq2: Set correct transceiver type for UltraScale projects 
Make sure that the axi_adxcvr instances are configured with the same
transceiver type as the util_adxcvr.

This is necessary for software to be able to detect the transceiver type
and support dynamic reconfiguration.

It is also necessary for correct eye scan support in the axi_adxcvr block.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2017-11-14 14:31:03 +01:00
Lars-Peter Clausen 46acdadb92 adrv9371x: Set correct transceiver type for UltraScale projects 
Make sure that the axi_adxcvr instances are configured with the same
transceiver type as the util_adxcvr.

This is necessary for software to be able to detect the transceiver type
and support dynamic reconfiguration.

It is also necessary for correct eye scan support in the axi_adxcvr block.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2017-11-14 14:31:03 +01:00
Lars-Peter Clausen caac2ce588 adrv9371x: zcu102: Fix lane mapping 
Fix the location assignment of the transceiver blocks to get the correct
lane mapping.

Note that the comments indicating the expected lane mapping are correct,
but the actual transceiver location assignments were not.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2017-11-14 14:31:03 +01:00
Lars-Peter Clausen f181e037cc adrv9371x: zcu102: Fix QPLL feedback divider 
The external reference clock runs at 122.88 MHz by default. This means that
the QPLL feedback divider needs to be set to 80 so that the VCO is inside
the locking range (9.8 GHz - 16.375 GHz).

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2017-11-14 14:31:03 +01:00
Adrian Costina 45f2fbf3c0 fmcjesdadc1: Update A10GX/A10SOC projects to the ADI JESD framework 2017-11-08 14:35:18 +02:00
AndreiGrozav 514e54287c zcu102 constraints description/cosmetic updates 2017-11-08 10:38:39 +02:00
AndreiGrozav 22808fa03c zcu102: Update to rev 1.0 2017-11-08 10:33:12 +02:00
Istvan Csomortani 7062785947 fmcomms2: Connect dac data underflow 
DAC data underflow from the DMA, was not connected to anything. This
signal should be connected to the util_rfifo, which will forward it to
the device core.
 2017-11-06 10:29:34 +00:00
Adrian Costina f692d7bc40 daq3: Disable start synchronization for the ADC DMA 
The ADC FIFO does not provide any sync output and for two channels it's not needed
 2017-11-01 09:31:19 +02:00
Adrian Costina 2b4b9d7bab daq2: Disable start synchronization for the ADC DMA 2017-10-31 17:16:08 +02:00
Istvan Csomortani e3ea51ade3 avl_dacfifo: Refactor the fifo 
+ Build both the read and write logic around an FSM
 + Consistent naming of registers and wires
 + Add support for burst lenghts higher than one, current burst lenght
is 64
 + Fix all the bugs, and make it work (first bring up with
adrv9371x/a10soc)
 2017-10-31 14:30:06 +00:00
Michael Hennerich 5b9e4cb692 daq2/zcu102: Pin Swap for ZCU102 Rev1.0 
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
 2017-10-30 11:09:20 +00:00
Adrian Costina 22df03f9a4 daq3: A10GX, overconstrained failing paths 2017-10-28 08:21:50 +01:00
Adrian Costina fe1adb6e4f daq3: A10GX, updated to the ADI JESD204 
- changed lane rate to 12.33Gbps
- added dac fifo
 2017-10-25 14:45:27 +01:00
Adrian Costina de5a21af80 daq2: A10GX, added additional interconnect pipelining 2017-10-23 16:39:58 +01:00
Matt Fornero e8bab0b45f adi_env: Normalize environment variables 
If the ADI_HDL_DIR or ADI_PHDL_DIR are set on Windows platforms, an
invalid TCL character (e.g. backslash) may be used as a file separator,
causing issues with the build / library scripts.

Normalize the paths before using them as global TCL variables.
 2017-10-23 12:15:14 +01:00
Adrian Costina 37323e3444 adrv9371x: A10GX, added extra pipelining in the interconnect in order to improve timing 2017-10-20 13:46:22 +01:00
Adrian Costina aa6af4e522 daq2: A10GX, added extra pipelining in the interconnect in order to improve timing 2017-10-20 13:45:05 +01:00
Adrian Costina 083962450a daq2: A10GX, connect dac_fifo_bypass to gpio 2017-10-19 16:07:18 +03:00
Adrian Costina e43056455c daq2: A10SOC, added dac fifo 2017-10-12 14:16:05 +03:00
Adrian Costina 72d9c1c6f2 daq2: A10GX, added dac fifo 2017-10-11 12:52:15 +03:00
Istvan Csomortani d9acdb8092 usdrx1/a10gx: Add external flash support 2017-10-06 08:47:24 +01:00
Istvan Csomortani baf8ec09a3 fmcjesdadc1/a10gx: Add external flash support 2017-10-06 08:46:22 +01:00
Istvan Csomortani df70a6605c daq3/a10gx: Add external falsh support 2017-10-06 08:45:33 +01:00
Istvan Csomortani be4e02aed9 adrv9371x/a10gx: Add external flash support 2017-10-06 08:43:58 +01:00
Adrian Costina d690a614c1 a10gx: Force all used tiles to high speed, in order to improve timing 2017-10-04 16:16:00 +01:00
AndreiGrozav 03e744f0f1 daq1_zed: Lower the adc and daq clock to 450MHz 
The FPGA fabric on zedboard is a -1 speadgrade (max bufg clk 464MHz)
 2017-10-04 13:01:14 +01:00
AndreiGrozav 7a3c4ab81f arradio: Changed ADC DMA buswidth connection to the DDR to 128 bits 
This fixes the bandwidth issue when data is streamed from the DDR and the system works at 61.44 MSPS
 2017-10-04 13:01:14 +01:00
STEVE KRAVATSKY ee01ea3736 daq2/a10gx: Add cfi_flash to qsys 
+ Add cfi_flash to qsys
   + Set nios reset vector to cfi_flash
 2017-10-04 11:30:29 +01:00
Istvan Csomortani a33f3178c2 adrv9371x/a10soc: For receive paths SYNC_TRANSFER must be enabled 2017-10-04 11:29:09 +01:00
Istvan Csomortani 899b8436ad arradio: Fix the last incorrect merge 2017-10-03 09:15:45 +01:00
Istvan Csomortani 89bd8b44d4 Merge branch 'dev' into hdl_2017_r1 2017-09-26 07:42:19 +01:00
AndreiGrozav 256dd87dd2 common/microzed: Enable PS CLK1 = 200MHz 2017-09-25 15:16:58 +03:00