Commit Graph

69 Commits (64c8fd7e5e9a90b9eb40e7a8ecb77d39f9661365)

Author SHA1 Message Date
Lars-Peter Clausen d7e87a60a9 Remove executable flag from non-executable files
All of these files are source code and are not executable standalone.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-28 17:56:07 +02:00
Adrian Costina b7ca17f02b scripts: Change adi_project_create to adi_project_xilinx for creating xilinx projects 2017-06-07 12:06:50 +03:00
Istvan Csomortani 84b2ad51e2 license: Add some clarification to the header license 2017-05-31 18:18:56 +03:00
Istvan Csomortani 85ebd3ca01 license: Update license terms in hdl source files
Fix a few gramatical error, fix the path of the top level license
files.
2017-05-29 09:55:41 +03:00
Istvan Csomortani 9055774795 all: Update license for all hdl source files
All the hdl (verilog and vhdl) source files were updated. If a file did not
have any license, it was added into it. Files, which were generated by
a tool (like Matlab) or were took over from other source (like opencores.org),
were unchanged.

New license looks as follows:

Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.

Each core or library found in this collection may have its own licensing terms.
The user should keep this in in mind while exploring these cores.

Redistribution and use in source and binary forms,
with or without modification of this file, are permitted under the terms of either
 (at the option of the user):

  1. The GNU General Public License version 2 as published by the
     Free Software Foundation, which can be found in the top level directory, or at:
https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html

OR

  2.  An ADI specific BSD license as noted in the top level directory, or on-line at:
https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
2017-05-17 11:52:08 +03:00
Istvan Csomortani bb0cdf2f5e fmcomms2: Update IP instantiations 2017-04-21 15:09:37 +03:00
Istvan Csomortani 1c23cf4621 all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
Rejeesh Kutty 8063ba2b66 make updates 2017-03-20 16:05:18 -04:00
Rejeesh Kutty c3c8c366d3 axi_ad9361- add receive init delay 2017-03-13 16:28:53 -04:00
Rejeesh Kutty 0ae79ca7ac move/rename - delay script belongs to ad9361 2017-03-10 12:44:32 -05:00
Rejeesh Kutty 452e5e5ce0 fmcomms2- add delay reporting for iodelay 2017-03-09 15:29:15 -05:00
Adrian Costina a36057679a fmcomms2: Update Makefiles 2017-01-13 14:16:21 +02:00
Istvan Csomortani 0cd608a7e2 lib_refactoring: Update Make files 2016-08-08 16:38:38 +03:00
Istvan Csomortani df36902713 lib_refactoring: Fix path of the IO macros 2016-08-08 15:07:19 +03:00
Adrian Costina d60bce654c Makefiles: Updated Makefiles so they run correctly with gnuwin32 tools 2016-08-05 15:16:04 +03:00
Rejeesh Kutty e42b4ea378 hdlmake- updates 2016-08-04 13:28:25 -04:00
Istvan Csomortani 7ca8e10004 make: Update Make files 2016-08-01 14:24:48 +03:00
Rejeesh Kutty 3006c5a223 make updates 2016-04-11 16:14:59 -04:00
Istvan Csomortani c051a578e5 fmcomms2: Delete unnecessary clock definition
The two clocks, rx_clk and ad9361_clk, are the same.
2015-11-20 19:35:37 +02:00
Istvan Csomortani 2345d29663 fmcomms2: Update make files 2015-11-11 11:15:45 +02:00
Istvan Csomortani a936ad607f fmcomms2/zc706: Delete unused files from file list 2015-11-11 11:14:58 +02:00
Istvan Csomortani c7e86528d6 fmcomms2/zc706: Cosmetic changes on constraints file 2015-11-11 11:14:16 +02:00
Adrian Costina 9d2b8809df Makefiles: Updated Makefiles 2015-10-23 10:44:27 +03:00
Istvan Csomortani 510f1cfdd9 fmcomms2_zc706: Update project with the new TDD sync interface 2015-09-09 12:35:22 +03:00
Rejeesh Kutty 026fad8853 fmcomm2- enable/txnrx- through devif 2015-08-27 11:41:58 -04:00
Istvan Csomortani 10d9de39a1 axi_ad9361/tdd: Update the synchronization logic
The master will regenerate a sync pulse periodically. The period can be defined by software.
2015-08-19 12:21:23 +03:00
Istvan Csomortani bcee3e04d4 fmcomms2_tdd: Update tdd_enabaled path
This line controls the mux, which switch between hdl and software (GPIO) control of the ENABLE/TXNRX pins.
Fix the broken path and change the name from "tdd_enable" to "tdd_enabled".
2015-08-19 12:14:05 +03:00
Istvan Csomortani d2c99acae8 fmcomms2/TDD: Update synchronization interface
Synchronization is done by a simple req/ack interface between a master and slave terminal.
2015-08-06 15:14:36 +03:00
Istvan Csomortani 8e631e56d6 fmcomms2: Add a synchronization interface for TDD mode.
Supported carrier are ZC706 and RFSOM.
The synchronization pulse is automatically generated by the master terminal, when TDD mode is enabled.
By default a terminal is slave, software must write  0x01 into TDD register 0x50.
2015-07-28 14:42:54 +03:00
Adrian Costina a7da779b94 Makefile: Updated Makefiles 2015-07-16 18:19:42 +03:00
Istvan Csomortani 1dcbf5e5a2 fmcomms2/zc706: Fix GPIO connections
Fix GPIO connections for the FREQCVT board.
2015-07-15 15:12:01 +03:00
Istvan Csomortani 46fa91d5be Makefile: Update Make files 2015-07-03 18:08:57 +03:00
Istvan Csomortani 0102e3e02c fmcomms2_ALL: Preserve backward compatibility for ENABLE/TXNRX control
By default the ENABLE/TXNRX pins are controlled by GPIOs, if the TDD module is enabled, the TDD FSM will take over the control of these two pins.
2015-07-01 13:54:01 +03:00
Lars-Peter Clausen 6862655b0d Add .gitattributes file
Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 11:07:10 +02:00
Istvan Csomortani 25f1ad73f0 fmcomms2/freqcvt: Update SPI interface I/O 2015-06-05 18:16:14 +03:00
Rejeesh Kutty f1e75963a2 fmcomms2: wfifo+pack changes 2015-06-05 09:20:50 -04:00
Istvan Csomortani 3b1ea7e528 axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch
598ece4c8d
2015-06-04 18:09:47 +03:00
Rejeesh Kutty a6cae6b477 iobuf: do is a system verilog keyword 2015-05-21 14:06:17 -04:00
Lars-Peter Clausen 6b9906b22b Refresh Makefiles
Re-generate the Makefiles after a small update to the generation script:
- Entries are sorted alphabetically
- Empty dependency lines are skipped

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 14:21:54 +02:00
Rejeesh Kutty 3e51d29f75 enable/txnrx- tdd changes 2015-05-18 14:28:20 -04:00
Adrian Costina c19749361d Makefiles: Updated makefiles to have as a result the programming file instead of the project file.
Also fixed altera projects dependencies
2015-05-18 17:22:46 +03:00
Istvan Csomortani d9a124b767 fmcomms2_zc706: TDD integration, initial commit. 2015-05-11 12:20:45 +03:00
Adrian Costina 949abcdc8f Makefile: Updated makefiles so that the project recipe does not depend on lib 2015-05-06 14:58:29 +03:00
Rejeesh Kutty c3dd9258e7 zc706: project mode 2015-05-04 10:25:12 -04:00
Rejeesh Kutty 62acd37fee zc706: project mode 2015-05-04 10:25:07 -04:00
Rejeesh Kutty 00cafd4df0 fmcomms2/zc706: add partial reconfiguration 2015-05-01 12:23:18 -04:00
Rejeesh Kutty 3641d8f714 fmcomms2/zc706: add partial reconfiguration 2015-05-01 12:23:11 -04:00
Rejeesh Kutty 75a81d67d8 fmcomms2/zc706: add partial reconfiguration 2015-05-01 12:23:07 -04:00
Adrian Costina dc2b37bd0c Makefile: Added top level Makefile. Modified behavior of clean and clean-all
Clean ran for a project will clean only the project files.
Clean-all ran for a project will clean also the library files on which the project depends.
The clean commands will only remove specific files and directories.

The top Makefile allows several options(per suggestion from jameyhicks):
make fmcomms1.zed will run "make all" in projects/fmcomms1/zed/
make clean will run "make clean" for all the projects
make clean-all will run "make clean" for all the projects and libraries
make lib will run "make all" for the library files
2015-04-17 17:22:38 +03:00
Adrian Costina 780455d68c Makefile: Updated makefiles. Added makefiles for altera 2015-04-09 17:57:06 +03:00